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公开(公告)号：US20240297240A1
公开(公告)日：2024-09-05
申请号：US18428306
申请日：2024-01-31
Applicant: STMicroelectronics International N.V.
Inventor： Voon Cheng NGWAN , Churn Weng YIM , Vincenzo ENEA
CPC classification number: H01L29/66734 , H01L29/401 , H01L29/407 , H01L29/7813
Abstract: A semiconductor substrate has a substrate trench extending from a front surface and including a lower part and an upper part. A first insulation layer lines the substrate trench, and a first conductive material is insulated from the semiconductor substrate by the first insulating layer to form a transistor field plate electrode. A gate trench in the first insulation layer defines an integral part of the first insulating layer surrounding the first conductive material in an upper part of the substrate trench. A second insulating layer lines the semiconductor substrate at the upper part of the substrate trench in the gate trench. A second conductive material fills the gate. The second conductive material forms a transistor gate electrode that is insulated from the semiconductor substrate by the second insulating layer and further insulated from the first conductive material by the integral part of the first insulating layer.
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公开(公告)号：US20240296899A1
公开(公告)日：2024-09-05
申请号：US18661914
申请日：2024-05-13
Applicant: STMicroelectronics International N.V.
CPC classification number: G11C29/38 , G11C7/1084 , G11C7/22 , G11C29/14 , G11C29/36 , G11C2029/1206 , G11C2029/3602 , H03K19/20
Abstract: A system includes a write-data register and a read-data register, each clocked by a clock signal, and a first-in-first-out (FIFO) buffer coupled between the write-data register and the read-data register, the FIFO buffer including latches configured to store data. The system further includes glue logic with first, second, and third logic circuits configured to generate an internal write enable signal, an internal read valid signal, and an internal read enable signal based on an operational mode of the system. The system is configured to be selectively switched between a normal operational mode, where the latches are accessed for reading and writing by a read enable signal and write enable signal based on a read address signal and a write address signal, and a transition testing mode, where the latches are tested using the internal write enable signal, the internal read enable signal, and the internal read valid signal.
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公开(公告)号：US20240289148A1
公开(公告)日：2024-08-29
申请号：US18582274
申请日：2024-02-20
Applicant: STMicroelectronics International N.V.
Inventor： Luigi DI MAGGIO , Ettore MIRTO
CPC classification number: G06F9/45529 , G06F9/54
Abstract: A method includes executing an application of a scripting language. The application of the scripting language uses first and second packages of an application programming interface (API). The first and second packages extend to each other. The method includes, from a class of the first package, calling and executing first native code of the API to implement a function of a method of the class of the first package. The first native code is in a programming language different from the scripting language. The executing the first native code of the API includes calling a method of a class of the second package. The called method of the class of the second package is executed using a virtual machine of the scripting language. The application of the scripting language may be a Java card application, and the programming language may be a C programming language.
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公开(公告)号：US20240288478A1
公开(公告)日：2024-08-29
申请号：US18436644
申请日：2024-02-08
Applicant: STMicroelectronics International N.V.
Inventor： Antonio Barcella , Mario Rotigni , Nicolas Bernard Grossier
CPC classification number: G01R23/005 , G01S19/13 , H03K5/26 , H03K19/20
Abstract: A method comprises receiving an input clock signal having a clock frequency band between a lower frequency limit value and an upper frequency limit value, dividing the clock frequency band in a set of frequency ranges having a set of frequency limit values that include the lower frequency limit value and the upper frequency limit value, comparing the frequency of the clock signal with the set of frequency limit values to produce comparison indicators having a first logic value when the measured frequency fails to exceed at least one frequency limit value and having a second logic value when the measured frequency exceeds the at least one frequency limit value, and, as a result of at least one of the logic values of comparison indicators having the second logic value, producing a global flag signal indicating that the measured frequency falls outside of a frequency range.
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公开(公告)号：US20240283736A1
公开(公告)日：2024-08-22
申请号：US18440216
申请日：2024-02-13
Applicant: STMicroelectronics International N.V.
Inventor： Lorenzo Re Fiorentin , Giampiero Borgonovo , Gianluca Di Carlo
IPC: H04L45/00 , H04L45/745 , H04L61/2546
CPC classification number: H04L45/566 , H04L45/745 , H04L61/2546
Abstract: A hardware network accelerator comprises a plurality of Ethernet communication interfaces, a plurality of memories, and a further memory. Each memory stores records comprising destination IP data identifying a destination IP address range. The further memory stores further records, wherein each record comprises next-hop data indicating a next-hop IP address, next-hop enable data, and network port data indicating an Ethernet communication interface. Each Ethernet communication interface is configured to obtain an IP packet, access in parallel the memories in order to read the records, select a record having a destination IP address range containing the destination IP address of the IP packet, read the further record associated with the selected record from the further memory, and select the indicated Ethernet communication interface. The selected Ethernet communication interface is configured to transmit an Ethernet frame comprising the IP packet based on the next-hop enable data and next-hop data.
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Patent Agency Ranking
公开(公告)号：US20240274572A1
公开(公告)日：2024-08-15
申请号：US18415006
申请日：2024-01-17
Applicant: STMicroelectronics International N.V.
Inventor： Jefferson Sismundo TALLEDO
IPC: H01L23/00 , H01L21/48 , H01L21/56 , H01L23/495
CPC classification number: H01L24/84 , H01L21/4842 , H01L21/561 , H01L23/49582 , H01L24/40 , H01L24/97 , H01L21/565 , H01L24/32 , H01L24/73 , H01L24/92 , H01L2224/32245 , H01L2224/40245 , H01L2224/73263 , H01L2224/84947 , H01L2224/92246 , H01L2224/97 , H01L2924/13091
Abstract: An etched leadframe includes separated frame portions, where each frame portion includes an intermediate region interposed between lead and die pad regions. An integrated circuit die is mounted to each die pad region. A clip is mounted to each integrated circuit die, wherein the clip includes a lead mounting portion mounted to the lead region of an adjacent frame portion and a bridge portion extending over the intermediate region of the adjacent frame portion and mounted to the die pad region of the adjacent frame portion. A first cut made through the frame portion of each etched leadframe at the intermediate region separates the lead and die pad regions without severing the bridge portion of each clip. A conductive layer is plated on full sidewalls of the lead and die pad regions exposed by the first cut. A second cut is then made through the bridge portion of each clip.
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公开(公告)号：US20240273344A1
公开(公告)日：2024-08-15
申请号：US18434549
申请日：2024-02-06
Applicant: STMicroelectronics International N.V.
Inventor： Filippo NACCARI , Angelo BOSCO
IPC: G06N3/047
CPC classification number: G06N3/047
Abstract: A processing device includes memory circuitry having stored therein a set of weight values and a threshold value and instructions which, when executed in the processing device, cause the processing device to apply a first artificial neural network (ANN) processing to a set of sensing signals, producing as a result a set of compressed representations of the sensing signals. The first ANN processing is trained to produce the set of compressed representations using a set of training signals distributed according to a set of training classes having an integer number L of classes. The instructions further cause the processing device to configure weight values of a plurality of computing units of a set of ANN processing circuits as a function of a set of weight values.
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公开(公告)号：US20240265152A1
公开(公告)日：2024-08-08
申请号：US18420024
申请日：2024-01-23
Applicant: STMicroelectronics International N.V.
Inventor： Alexandre Tramoni , Fabrice Romain
IPC: G06F21/71
CPC classification number: G06F21/71
Abstract: The present description concerns an integrated circuit comprising at least two secure circuits having similar functions but respecting or complying with different security schemes.
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公开(公告)号：US20240256154A1
公开(公告)日：2024-08-01
申请号：US18420263
申请日：2024-01-23
Applicant: STMicroelectronics International N.V.
Inventor： Michael GIOVANNINI
IPC: G06F3/06
CPC classification number: G06F3/0625 , G06F3/0634 , G06F3/0673
Abstract: A system includes a memory formed by memory units accessible in write mode and in read mode. Each memory unit includes an array of memory cells and a peripheral circuit of access to the memory cells. Each memory unit is configurable in a first operating mode and a second operating mode. The array of memory cells are set in the first operating mode and the second operating modes to retain data until a subsequent powering off of the memory unit. The peripheral circuit is powered in the first operating mode and is not powered in the second operating mode. A controller configures any memory unit of the memory having undergone no write or read access for a determined time period to be in the second operating mode.
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公开(公告)号：US20240255386A1
公开(公告)日：2024-08-01
申请号：US18161674
申请日：2023-01-30
Applicant: STMicroelectronics International N.V.
Inventor： Federico RIZZARDINI , Lorenzo BRACCO
CPC classification number: G01M99/005 , G06N20/00
Abstract: A sensor unit is coupled to a machine and configured to detect anomalous behavior of the machine. The sensor unit includes a low power microcontroller that learns to recognize a plurality of operations of the machine. The sensor unit generates mean vector and inverse of a Cholesky decomposition matrix for each operation. During a detection mode the sensor unit computes a Mahalanobis distance for each feature vector, mean vector and first matrix. The sensor unit detects anomalous behavior or classifies the operation of the machine based on the Mahalanobis distances.
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