公开(公告)号：US20250079162A1

公开(公告)日：2025-03-06

申请号：US18952021

申请日：2024-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Ya-Wen Chiu ,  Cheng-Po Chau ,  Yi Che Chan ,  Chih Ping Liao ,  YungHao Wang ,  Sen-Hong Syue

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66

Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

公开(公告)号：US20250076594A1

公开(公告)日：2025-03-06

申请号：US18543459

申请日：2023-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tung-Liang Shao ,  Yi-Jan Lin ,  Yu-Sheng Huang ,  Tsung-Fu Tsai ,  Chao-Jen Wang ,  Szu-Wei Lu

IPC: G02B6/42 ,  G02B6/12 ,  G02B6/13

Abstract: Optical devices and methods of manufacture are presented in which a multi-tier connector is utilized to transmit and receive optical signals to and from an optical device. In embodiments a multi-tier connection unit receives optical signals from outside of an optical device, wherein the optical signals are originally in multiple levels. The multi-tier connection unit then routes the optical signals into a single level of optical components.

公开(公告)号：US12245526B2

公开(公告)日：2025-03-04

申请号：US18475978

申请日：2023-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chao Lin ,  Yuan-Tien Tu ,  Shao-Ming Yu ,  Tung-Ying Lee

IPC: H10N70/00 ,  H10N70/20

Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating. The protection coating forms a first interface with the phase change element. The first interface has a first slope at a first position and a second slope at a second position higher than the first position, the second slope is different from the first slope.

公开(公告)号：US12243829B2

公开(公告)日：2025-03-04

申请号：US17808889

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/16 ,  H01L23/31

Abstract: A semiconductor package and methods of forming the same are disclosed. In an embodiment, a package includes a substrate; a first die disposed within the substrate; a redistribution structure over the substrate and the first die; and an encapsulated device over the redistribution structure, the redistribution structure coupling the first die to the encapsulated device.

公开(公告)号：US12243824B2

公开(公告)日：2025-03-04

申请号：US18525958

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu

IPC: H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.

公开(公告)号：US12243783B2

公开(公告)日：2025-03-04

申请号：US17232898

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Lin Huang ,  Li-Li Su ,  Yee-Chia Yeo ,  Chii-Horng Li

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/033 ,  H01L21/285 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

公开(公告)号：US12243707B2

公开(公告)日：2025-03-04

申请号：US18448026

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Heng Yen ,  Jen-Chung Chiu ,  Tai-Kun Kao ,  Lu-Hsun Lin ,  Tsung-Min Lin

IPC: H01J37/08 ,  H01J37/317 ,  H01J37/32

Abstract: The current disclosure is directed to a repellent electrode used in a source arc chamber of an ion implanter. The repellent electrode includes a shaft and a repellent body having a repellent surface. The repellent surface has a surface shape that substantially fits the shape of the inner chamber space of the source arc chamber where the repellent body is positioned. A gap between the edge of the repellent body and the inner sidewall of the source arc chamber is minimized to a threshold level that is maintained to avoid a short between the conductive repellent body and the conductive inner sidewall of the source arc chamber.

公开(公告)号：US12240076B2

公开(公告)日：2025-03-04

申请号：US18362134

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien Hua Shen ,  Hsun-Chung Kuang

IPC: B24B53/017 ,  B24B53/12

Abstract: A pad conditioner for conditioning a polishing surface of a polishing pad includes a conditioning disk, a disk holder, and a disk arm. The conditioning disk includes a substrate plate and at least two abrasive segments. The conditioning disk includes at least one channel by which debris and spent slurry may be evacuated. The abrasive segments are on a surface of the substrate plate, and form at least one channel segment therebetween. Each channel segment extends from about the center of the surface to substantially the outer rim of the substrate plate. The disk holder to which the conditioning disk is mounted includes a through hole. The disk arm to which the conditioning disk is mounted includes an opening in fluid communication with the at least one channel segment via the through hole for evacuating the debris and spent slurry by a vacuum module.

公开(公告)号：US20250072065A1

公开(公告)日：2025-02-27

申请号：US18405526

申请日：2024-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hung CHANG ,  Shih-Cheng CHEN ,  Chia-Hao YU ,  Chia-Cheng TSAI ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L21/764 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A device includes: a substrate; a stack of semiconductor channels on the substrate; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; and a hybrid structure between the source/drain region and the substrate. The hybrid structure includes: a first semiconductor layer under the source/drain region; and an isolation region extending vertically from an upper surface of the first semiconductor layer to a level above a bottom surface of the first semiconductor layer.

公开(公告)号：US20250070085A1

公开(公告)日：2025-02-27

申请号：US18401949

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsang-Jiuh Wu ,  Shih-Che Lin ,  Cheng-Chun Tsai ,  Ping-Jung Wu ,  Hao-Wen Ko

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00

Abstract: A method includes: forming first bond pads along a wafer; bonding a first die to a first set of the first bond pads, the first die being electrically connected to the wafer; depositing a gap-fill dielectric over the wafer and around the first die; forming openings in the gap-fill dielectric; forming first active through vias in physical contact with the second set of the first bond pads and first dummy through vias in physical contact with the third set of the first bond pads, the first active through vias being electrically connected to the wafer, the first dummy through vias being electrically isolated from the wafer; forming second bond pads along the first die, the first active through vias, and the first dummy through vias; and bonding a second die to the first die and to a first active via of the first active through vias.