公开(公告)号：US08970262B2

公开(公告)日：2015-03-03

申请号：US13978373

申请日：2012-01-09

申请人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

发明人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

IPC分类号： H03B1/00 ,  H03K3/00 ,  H01L27/088 ,  H03K17/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423 ,  H01L27/098 ,  H01L29/06

CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

摘要： Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 公开了一种包括具有负载路径的第一半导体器件和多个第二晶体管的半导体器件布置，每个第二晶体管具有在第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接，每个第二晶体管的控制端连接到其它第二晶体管之一的负载端，第二晶体管中的一个 晶体管的控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US08866253B2

公开(公告)日：2014-10-21

申请号：US13362038

申请日：2012-01-31

申请人： Rolf Weis ,  Gerald Deboy ,  Michael Treu ,  Armin Willmeroth ,  Hans Weber

发明人： Rolf Weis ,  Gerald Deboy ,  Michael Treu ,  Armin Willmeroth ,  Hans Weber

IPC分类号： H01L27/00

CPC分类号： H01L27/0207 ,  H01L21/84 ,  H01L21/845 ,  H01L27/06 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/4236 ,  H01L29/78 ,  H03K17/063 ,  H03K17/102

摘要： A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.

摘要翻译： 半导体器件布置包括具有负载路径的第一半导体器件和多个第二半导体器件，每个第二半导体器件具有在第一和第二负载端子与控制端子之间的负载路径。 第二半导体器件的负载路径串联连接并与第一半导体器件的负载路径串联连接。 每个第二半导体器件的控制端子连接到其它第二半导体器件之一的负载端子，并且其中一个第二半导体器件的控制端子连接到第一半导体器件的负载端子之一。 每个第二半导体器件具有至少一个器件特性。 第二半导体器件中的至少一个的至少一个器件特征与第二半导体器件中的其它器件的相应器件特性不同。

公开(公告)号：US20140062544A1

公开(公告)日：2014-03-06

申请号：US13978373

申请日：2012-01-09

申请人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

发明人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

IPC分类号： H01L27/088 ,  H03K17/06

CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

摘要： Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 公开了一种包括具有负载路径的第一半导体器件和多个第二晶体管的半导体器件布置，每个第二晶体管具有在第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接，每个第二晶体管的控制端连接到其它第二晶体管之一的负载端，第二晶体管中的一个 晶体管的控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US08530300B2

公开(公告)日：2013-09-10

申请号：US12842488

申请日：2010-07-23

申请人： Joachim Weyers ,  Armin Willmeroth ,  Anton Mauder ,  Franz Hirler

发明人： Joachim Weyers ,  Armin Willmeroth ,  Anton Mauder ,  Franz Hirler

IPC分类号： H01L21/8238

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/8613 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of forming a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type, and a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type.

摘要翻译： 公开了一种形成具有第一掺杂类型的漂移区和第二掺杂型的补偿区的半导体器件的方法，以及具有第一掺杂类型的漂移区和第二掺杂类型的补偿区的半导体器件。

公开(公告)号：US08492771B2

公开(公告)日：2013-07-23

申请号：US11862661

申请日：2007-09-27

申请人： Michael Rüb ,  Michael Treu ,  Armin Willmeroth ,  Franz Hirler

发明人： Michael Rüb ,  Michael Treu ,  Armin Willmeroth ,  Franz Hirler

IPC分类号： H01L29/15 ,  H01L31/0312

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41775 ,  H01L29/66068

摘要： A semiconductor device includes a first semiconductor substrate of a first band-gap material and a second semiconductor substrate of a second band-gap material. The second band-gap material has a lower band-gap than the first band-gap material. A heterojunction is formed between the first semiconductor substrate and the second semiconductor substrate substantially in a first plane. The semiconductor device further includes, in a cross-section which is perpendicular to the first plane, a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type both of which extend from the second semiconductor substrate at least partially into the first semiconductor substrate. The first and second semiconductor regions are spaced in the first semiconductor substrate from each other in a direction parallel to the first plane by a first distance which is arranged in an area proximate to the heterojunction and which is larger than a second distance which is arranged in an area distal to the heterojunction.

摘要翻译： 半导体器件包括第一带隙材料的第一半导体衬底和第二带隙材料的第二半导体衬底。 第二带隙材料具有比第一带隙材料低的带隙。 基本上在第一平面中，在第一半导体衬底和第二半导体衬底之间形成异质结。 所述半导体器件还包括垂直于所述第一平面的横截面，所述第一导电类型的第一半导体区域和所述第一导电类型的第二半导体区域从所述第二半导体衬底至少部分地延伸 进入第一半导体衬底。 第一和第二半导体区域在第一半导体衬底中沿平行于第一平面的方向彼此间隔开第一距离，第一距离布置在接近异质结的区域中，并且大于第二距离 远离异质结的区域。

公开(公告)号：US20120175635A1

公开(公告)日：2012-07-12

申请号：US13275151

申请日：2011-10-17

申请人： Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

发明人： Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

IPC分类号： H01L27/06 ,  H01L29/778 ,  H01L29/788 ,  H01L29/20 ,  H01L29/161 ,  H01L27/088 ,  H01L27/098

CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

摘要： A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 半导体器件布置包括具有负载路径的第一半导体器件和多个第二晶体管，每个具有第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接。 每个第二晶体管的控制端连接到其它第二晶体管的负载端子。 第二晶体管中的一个具有其控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US08110868B2

公开(公告)日：2012-02-07

申请号：US11435979

申请日：2006-05-17

申请人： Frank Dieter Pfirsch ,  Armin Willmeroth ,  Anton Mauder ,  Stefan Sedlmaier

发明人： Frank Dieter Pfirsch ,  Armin Willmeroth ,  Anton Mauder ,  Stefan Sedlmaier

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4916 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/872

摘要： A semiconductor component having a semiconductor body is disclosed. In one embodiment, the semiconductor component includes a drift zone of a first conductivity type, a drift control zone composed of a semiconductor material which is arranged adjacent to the drift zone at least in places, a dielectric which is arranged between the drift zone and the drift control zone at least in places. A quotient of the net dopant charge of the drift control zone, in an area adjacent to the accumulation dielectric and the drift zone, divided by the area of the dielectric arranged between the drift control zone and the drift zone is less than the breakdown charge of the semiconductor material in the drift control zone.

摘要翻译： 公开了一种具有半导体本体的半导体部件。 在一个实施例中，半导体部件包括第一导电类型的漂移区，由半导体材料构成的漂移控制区，该半导体材料至少位于与漂移区相邻的位置处，布置在漂移区和 漂移控制区至少在地方。 漂移控制区的净掺杂剂电荷在与积聚电介质和漂移区相邻的区域除以布置在漂移控制区和漂移区之间的介质的面积除以小于 漂移控制区中的半导体材料。

公开(公告)号：US20110189839A1

公开(公告)日：2011-08-04

申请号：US13085196

申请日：2011-04-12

申请人： Armin Willmeroth ,  Franz Hirler

发明人： Armin Willmeroth ,  Franz Hirler

IPC分类号： H01L21/20

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/8083

摘要： A semiconductor device with a semiconductor body and method for its production is disclosed. The semiconductor body includes drift zones of epitaxially grown semiconductor material of a first conduction type. The semiconductor body further includes charge compensation zones of a second conduction type complementing the first conduction type, which are arranged laterally adjacent to the drift zones. The charge compensation zones are provided with a laterally limited charge compensation zone doping, which is introduced into the epitaxially grown semiconductor material. The epitaxially grown semiconductor material includes 20 to 80 atomic % of the doping material of the drift zones and a doping material balance of 80 to 20 atomic % introduced by ion implantation and diffusion.

摘要翻译： 公开了一种半导体器件及其制造方法。 半导体本体包括第一导电类型的外延生长的半导体材料的漂移区。 半导体本体还包括与第一导电类型相互补充的第二导电类型的电荷补偿区，它们被布置成横向邻近漂移区。 电荷补偿区带有横向有限的电荷补偿区掺杂，其被引入外延生长的半导体材料中。 外延生长的半导体材料包括漂移区的掺杂材料的20至80原子％和通过离子注入和扩散引入的80至20原子％的掺杂材料平衡。

公开(公告)号：US20110133262A1

公开(公告)日：2011-06-09

申请号：US12962780

申请日：2010-12-08

申请人： Uwe Wahl ,  Armin Willmeroth

发明人： Uwe Wahl ,  Armin Willmeroth

IPC分类号： H01L29/78

CPC分类号： H01L29/402 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7817 ,  H01L29/7823

摘要： A semiconductor component includes a body with a drift zone, a source zone, a body zone, and a drain zone. A gate forms a MOS structure with the drift zone, with the source zone and with the body zone. An edge termination between the lateral edge and the MOS structure includes a plurality of field rings which enclose the MOS structure. The lateral edge is at the same potential as the drift zone, and the edge termination reduces voltage between the lateral edge and the source zone. A horizontally extending edge plate is disposed at the front side between the lateral edge and the edge termination. The edge plate is at the same potential as the drift zone and forms a plate capacitor structure including a field plate lying above the edge plate.

摘要翻译： 半导体部件包括具有漂移区的物体，源区，体区和排水区。 门形成具有漂移区的MOS结构，源区和身体区。 横向边缘和MOS结构之间的边缘终止包括包围MOS结构的多个场环。 横向边缘处于与漂移区相同的电位，并且边缘终止减小了侧边缘和源区之间的电压。 水平延伸的边缘板设置在侧边缘和边缘终端之间的前侧。 边缘板处于与漂移区相同的电位，并形成包括位于边缘板上方的场板的平板电容器结构。

公开(公告)号：US07910983B2

公开(公告)日：2011-03-22

申请号：US12241947

申请日：2008-09-30

申请人： Armin Willmeroth ,  Michael Treu

发明人： Armin Willmeroth ,  Michael Treu

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

摘要： A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which is dielectrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode.

摘要翻译： 描述了具有增加的栅 - 漏电容的MOS晶体管。 一个实施例提供了第一导电类型的漂移区。 至少一个晶体管单元具有体区，通过体区与漂移区分离的源极区以及邻近体区设置并通过栅介质与体区介电绝缘的栅电极。 在漂移区域中布置有至少一个第一导电类型的补偿区域。 至少一个反馈电极被布置在与身体区隔一定距离处，该区域通过反馈电介质与漂移区介电绝缘，并且与电极导电连接。