公开(公告)号：US6136649A

公开(公告)日：2000-10-24

申请号：US416389

申请日：1999-10-12

申请人： Angela T. Hui ,  Wenge Yang ,  Kashmir Sahota ,  Mark T. Ramsbey ,  Suzette K. Pangrle ,  Minh Van Ngo

发明人： Angela T. Hui ,  Wenge Yang ,  Kashmir Sahota ,  Mark T. Ramsbey ,  Suzette K. Pangrle ,  Minh Van Ngo

IPC分类号： H01L21/311 ,  H01L21/336 ,  H01L21/8247

CPC分类号： H01L27/11521 ,  H01L21/31116 ,  H01L29/66825

摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane (CH.sub.3 F)/oxygen (O.sub.2) etch chemistry is used to selectively remove the ARC layer. The CH.sub.3 F/O.sub.2 etch chemistry etches the ARC layer at a rate which is significantly faster than the etch rates of the dielectric layer or the tungsten contacts.

摘要翻译： 本发明提供一种用于在基板表面上从电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨触点。 在一个实施方案中，使用氟甲烷（CH 3 F）/氧（O 2）蚀刻化学物质来选择性地除去ARC层。 CH3F / O2蚀刻化学蚀刻ARC层的速度明显快于介电层或钨触点的蚀刻速率。

公开(公告)号：US5981364A

公开(公告)日：1999-11-09

申请号：US568195

申请日：1995-12-06

申请人： Mark T. Ramsbey ,  Hsingya Arthur Wang ,  Yu Sun

发明人： Mark T. Ramsbey ,  Hsingya Arthur Wang ,  Yu Sun

IPC分类号： H01L21/28 ,  H01L29/49

CPC分类号： H01L21/28035 ,  H01L29/4925

摘要： Disclosed herein is a method of forming a silicon gate stack onto a silicon substrate for a silicon device. The method of forming the silicon gate stack comprises the steps of growing an oxide layer onto the silicon substrate, depositing a thin layer of silicon to form a thin layer of silicon over the oxide layer, depositing a thick layer of silicon over the thin layer of silicon, and introducing impurities into only the thick layer of silicon to form a silicon gate whereby the silicon gate includes the thin layer of silicon and the thick layer of silicon having the impurities. The impurities being introduced with a concentration, the impurities concentration and the thick layer thickness impeding an encroachment by the oxide layer into the silicon gate during application of a protective screen oxide layer around the silicon gate stack.

摘要翻译： 本文公开了一种在硅器件的硅衬底上形成硅栅叠层的方法。 形成硅栅极堆叠的方法包括以下步骤：在硅衬底上生长氧化物层，沉积薄层的硅以在氧化物层上形成薄的硅层，在薄层上沉积厚的硅层 硅，并且将杂质引入仅硅的厚层中以形成硅栅极，由此硅栅极包括硅的薄层和具有杂质的厚的硅层。 引入浓度的杂质，杂质浓度和厚层厚度在施加硅栅堆叠周围的保护性屏蔽氧化物层时阻碍氧化层侵入硅栅中。

公开(公告)号：US5966618A

公开(公告)日：1999-10-12

申请号：US36288

申请日：1998-03-06

申请人： Yu Sun ,  Tuan D. Pham ,  Mark T. Ramsbey ,  Chi Chang

发明人： Yu Sun ,  Tuan D. Pham ,  Mark T. Ramsbey ,  Chi Chang

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L27/08 ,  H01L27/105

CPC分类号： H01L21/76221 ,  H01L27/105

摘要： A method of providing thick and thin oxide structures reduces step changes between a core region and a peripheral region on an integrated circuit. Thin LOCOS structures are provided in a core region of a flash memory device, and thick LOCOS structures are provided in a peripheral region of the flash memory device. The device and process are not as susceptible to "race track" problems, "oxide" bump problems, and "stringer" problems. The process utilizes two separate nitride or hard mask layers.

摘要翻译： 提供厚且薄的氧化物结构的方法减小了集成电路上的芯区域和周边区域之间的阶跃变化。 在闪速存储器件的核心区域中提供了薄的LOCOS结构，并且在闪速存储器件的外围区域中提供了厚的LOCOS结构。 设备和过程不容易受到“赛道”问题，“氧化物”碰撞问题和“纵梁”问题的影响。 该方法利用两个分开的氮化物或硬掩模层。

公开(公告)号：US07972948B2

公开(公告)日：2011-07-05

申请号：US12880541

申请日：2010-09-13

申请人： Weidong Qian ,  Mark T. Ramsbey ,  Tazrien Kamal

发明人： Weidong Qian ,  Mark T. Ramsbey ,  Tazrien Kamal

IPC分类号： H01L21/22

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568

摘要： A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity.

摘要翻译： 存储器件包括多个存储器单元和多个位线。 每个位线包括具有第一宽度和第一深度的第一区域和具有第二宽度和第二深度的第二区域，其中第一宽度小于第二宽度。 第一区域可以包括n型杂质，第二区域可以包括p型杂质。

公开(公告)号：US20100330762A1

公开(公告)日：2010-12-30

申请号：US12880541

申请日：2010-09-13

申请人： Weidong Qian ,  Mark T. Ramsbey ,  Tazrien Kamal

发明人： Weidong Qian ,  Mark T. Ramsbey ,  Tazrien Kamal

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568

摘要： A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity,

摘要翻译： 存储器件包括多个存储器单元和多个位线。 每个位线包括具有第一宽度和第一深度的第一区域和具有第二宽度和第二深度的第二区域，其中第一宽度小于第二宽度。 第一区域可以包括n型杂质，第二区域可以包括p型杂质，

公开(公告)号：US07432178B2

公开(公告)日：2008-10-07

申请号：US11254769

申请日：2005-10-21

申请人： Angela T. Hui ,  Jean Yang ,  Yu Sun ,  Mark T. Ramsbey ,  Weidong Qian

发明人： Angela T. Hui ,  Jean Yang ,  Yu Sun ,  Mark T. Ramsbey ,  Weidong Qian

IPC分类号： H01L21/04

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.

摘要翻译： 公开了一种用于执行位线植入的方法。 该方法包括在半导体器件的氧化物 - 氮化物 - 氧化物堆叠上形成一组结构。 该组结构的每个结构包括多晶硅部分和硬掩模部分。 该组结构的第一结构与该组结构的第二结构分开小于100纳米。 该方法还包括使用第一结构和第二结构来隔离位线植入物的半导体器件的一部分。

公开(公告)号：US07414277B1

公开(公告)日：2008-08-19

申请号：US11112884

申请日：2005-04-22

申请人： Ashot Melik-Martirosian ,  Takashi Orimoto ,  Mark T. Ramsbey

发明人： Ashot Melik-Martirosian ,  Takashi Orimoto ,  Mark T. Ramsbey

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of raised bitlines, where the bitlines have a lower portion formed by a first process and an upper portion formed by a second process.

摘要翻译： 提供了存储器件和制造方法。 存储器件包括设置在半导体衬底上的半导体衬底和电荷俘获介质堆叠。 栅电极设置在电荷捕获电介质堆叠之上，其中栅极电极限定半导体衬底的一部分内的沟道。 存储装置包括一对升高的位线，其中位线具有由第一工艺形成的下部分和由第二工序形成的上部部分。

公开(公告)号：US07067377B1

公开(公告)日：2006-06-27

申请号：US10812703

申请日：2004-03-30

申请人： Jaeyong Park ,  Hidehiko Shiraiwa ,  Satoshi Torii ,  Mark T. Ramsbey

发明人： Jaeyong Park ,  Hidehiko Shiraiwa ,  Satoshi Torii ,  Mark T. Ramsbey

IPC分类号： H01L21/336

CPC分类号： H01L29/42352 ,  H01L27/105 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

摘要： Systems and methods of fabricating a U-shaped memory device with a recessed channel and a segmented/separated ONO layer are provided. Multibit operation is facilitated by a separated ONO layer, which includes a charge trapping region on sidewalls of polysilicon gate structures adjacent to source/drain regions. Programming and erasing of the memory cells is facilitated by the relatively short distance between acting source regions and the gate. Additionally, short channel effects are mitigated by a relatively long U-shaped channel region that travels around the recessed polysilicon gate thereby adding a depth dimension to the channel length.

摘要翻译： 提供了制造具有凹陷通道和分段/分离的ONO层的U形存储器件的系统和方法。 通过分离的ONO层促进多位操作，该ONO层包括邻近源极/漏极区的多晶硅栅极结构的侧壁上的电荷俘获区域。 存储器单元的编程和擦除由于作用源极区域和栅极之间的距离相对较短而便于实现。 此外，通过在凹陷多晶硅栅极周围移动的相对较长的U形沟道区域减轻了短沟道效应，从而增加了沟道长度的深度尺寸。

公开(公告)号：US06987048B1

公开(公告)日：2006-01-17

申请号：US10635781

申请日：2003-08-06

申请人： Ning Cheng ,  Hiroyuki Kinoshita ,  Jeff P. Erhardt ,  Mark T. Ramsbey ,  Cyrus Tabery ,  Jean Yee-Mei Yang

发明人： Ning Cheng ,  Hiroyuki Kinoshita ,  Jeff P. Erhardt ,  Mark T. Ramsbey ,  Cyrus Tabery ,  Jean Yee-Mei Yang

IPC分类号： H01L21/8247

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11568 ,  Y10S438/954

摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate, a bottom dielectric, a charge storing layer, and a top dielectric in a stacked gate configuration. Silicided buried bitlines, which function as a source and a drain, are formed within the substrate. The silicided bitlines have a reduced resistance, which greatly reduces the number of bitline contacts necessary in an array of memory devices.

摘要翻译： 提供了存储器件和制造方法。 存储器件包括半导体衬底，底部电介质，电荷存储层和堆叠栅极配置中的顶部电介质。 用作源极和漏极的硅化掩埋位线形成在衬底内。 硅化的位线具有降低的电阻，这大大减少了存储器件阵列中所需的位线接触的数量。

公开(公告)号：US06962849B1

公开(公告)日：2005-11-08

申请号：US10729732

申请日：2003-12-05

申请人： Tazrien Kamal ,  Weidong Qian ,  Kouros Ghandehari ,  Taraneh Jamali-Beh ,  Mark T. Ramsbey ,  Ashok M. Khathuria

发明人： Tazrien Kamal ,  Weidong Qian ,  Kouros Ghandehari ,  Taraneh Jamali-Beh ,  Mark T. Ramsbey ,  Ashok M. Khathuria

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Spacers are utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.

摘要翻译： 公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。 在形成过程中使用间隔物来减小存储器中的掩埋位线的尺寸，这适用于存储用于计算机等的数据。 较小（例如较窄）的位线有助于增加打包密度，同时保持位线之间的有效通道长度。 位线之间的间隔允许存储在电荷俘获层内的通道上方的双位保持充分分离，以便彼此不干扰。 以这种方式，一个位可以被操作（例如，用于读取，写入或擦除操作）而基本上或不利地影响另一个位。 此外，保留位分离，并且减轻了可能由窄通道产生的漏电流，串扰以及其他不利影响，并且允许存储器件根据需要进行操作。