公开(公告)号：US07278072B2

公开(公告)日：2007-10-02

申请号：US10429579

申请日：2003-05-05

Applicant: Johann Pfeiffer ,  Helmut Fischer

Inventor： Johann Pfeiffer ,  Helmut Fischer

IPC: G11C29/26 ,  G11C29/50

CPC classification number: G11C29/12 ,  G11C11/401 ,  G11C29/40 ,  G11C2029/0405

Abstract: The testing of a RAM memory circuit containing a multiplicity of memory cells can in each case be selected in groups of n≧1 memory cells by using an applied address information item in order to write in or read out groups of in each case n data. According to the invention, in a test write cycle, a plurality i=j*m of the memory cell groups are selected, where j and m are in each case integers ≧2, and the same datum is written into all the memory cells of in each case m selected memory cell groups. In a subsequent read cycle, the i memory cell groups selected in the write cycle are selected and read in a sequence such that the read-out data groups from in each case m memory cell groups at which the same datum was written in are provided simultaneously or in direct succession as a read data block comprising m*n data. Each time a read data block is provided, a compressed test result is determined and provided; the result indicates if all m*n data of the read data block provided correspond to the datum written therein.

Abstract translation: 在每种情况下，通过使用应用的地址信息项来选择包含多个存储器单元的RAM存储器电路的测试，以便在n个= 1个存储器单元的组中写入或读出在每种情况下的n个数据组 。 根据本发明，在测试写入周期中，选择存储单元组的多个i = j * m，其中j和m在每种情况下都是> = 2，并且相同的数据被写入所有存储单元 在每种情况下m个选择的存储单元组。 在随后的读取周期中，以写入周期中选择的i个存储器单元组被选择并读取，使得从每个情况读出数据组m个记录相同数据的存储单元组同时被提供 或作为包含m * n个数据的读取数据块的直接连续。 每次读取数据块时，都会确定并提供压缩测试结果; 结果指示所提供的读取数据块的所有m * n数据是否对应于其中写入的数据。

公开(公告)号：US20070210433A1

公开(公告)日：2007-09-13

申请号：US11371204

申请日：2006-03-08

Applicant: Rajesh Subraya ,  Helmut Fischer ,  Ingo Wennemuth ,  Minka Gospodinova ,  Jochen Thomas

Inventor： Rajesh Subraya ,  Helmut Fischer ,  Ingo Wennemuth ,  Minka Gospodinova ,  Jochen Thomas

IPC: H01L23/02 ,  H01L21/00

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention provides an integrated device comprising a plurality of non-individually-encapsulated chip arrangements, each of which having a plurality of contact elements for contacting a contact pad, wherein the plurality of chip arrangements are stacked on each other such that the respective contact elements provide electrical connections to the respective chip arrangement, and a common integral mold arranged to encapsulate the plurality of stacked chip arrangements.

Abstract translation: 本发明提供了一种集成器件，其包括多个非单独封装的芯片布置，每个芯片布置具有用于接触接触焊盘的多个接触元件，其中所述多个芯片布置彼此堆叠，使得各个接触元件 提供到相应芯片布置的电连接，以及布置成封装多个堆叠芯片布置的公共整体模具。

公开(公告)号：US20070186434A1

公开(公告)日：2007-08-16

申请号：US11599627

申请日：2006-11-14

Applicant: Helmut Fischer

Inventor： Helmut Fischer

IPC: G01B3/22

CPC classification number: G01B7/105

Abstract: The invention relates to a Measuring probe for a device for the measurement of the thickness of thin layers, with a housing (14) comprising at least one sensor element (17), which is accepted along a longitudinal axis (16) of the housing (14) at least slightly movable to the housing (14) and with a contact spherical cap (21) assigned to the at least one sensor element (17) for setting the measuring probe (11) onto a surface of a measuring object, whereby in that the at least one sensor element (17) is accepted by a holding element (18)—along the longitudinal axis (16) of the housing (14)—which is designed spring-loaded resiliently and which is fastened on the housing (14).

Abstract translation: 本发明涉及一种用于测量薄层厚度的装置的测量探针，其中壳体（14）包括至少一个传感器元件（17），沿着壳体的纵向轴线（16）接受 14）至少可移动到壳体（14）并且具有分配给至少一个传感器元件（17）的接触球形盖（21），用于将测量探针（11）设置在测量对象的表面上， 所述至少一个传感器元件（17）被所述壳体（14）的纵向轴线（16）接受，所述保持元件（18）被弹性地设计为弹簧加载并且被紧固在所述壳体（14）上 ）。

公开(公告)号：US20060284089A1

公开(公告)日：2006-12-21

申请号：US11454486

申请日：2006-06-16

Applicant: Helmut Fischer

Inventor： Helmut Fischer

IPC: G21K7/00

CPC classification number: G01B7/105

Abstract: The invention relates to a calibration standard, especially for the calibration of devices for the non-destructive measurement of the thickness of thin layers, with a carrier layer (12) consisting of a basic material and a standard (17) applied on the carrier layer (12), said standard having the thickness of the layer to be measured at which the device is to be calibrated, with the carrier layer (12) comprising a plane-parallel measuring surface (16) to its bearing surface (14), that the standard (17) comprises a bearing surface (18) plane-parallel with its measuring surface (19) for bearing on the measuring surface (16) of the carrier layer (12), and that the standard (17) is permanently provided on the carrier layer (12) by means of plating by rubbing.

Abstract translation: 本发明涉及一种校准标准，特别是用于校准用于薄层厚度的非破坏性测量的装置，其中载体层（12）由施加在载体层上的基本材料和标准物（17）组成， （12），所述标准具有要被校准的待测量层的厚度，载体层（12）包括与其支承表面（14）的平面平行的测量表面（16），所述载体层 标准（17）包括与其测量表面（19）平行平行的支承表面（18），用于承载在载体层（12）的测量表面（16）上，并且标准件（17）永久地设置在 载体层（12）通过摩擦电镀。

公开(公告)号：US07072233B2

公开(公告)日：2006-07-04

申请号：US10850817

申请日：2004-05-21

Applicant: Ruediger Brede ,  Dominique Savignac ,  Helmut Fischer

Inventor： Ruediger Brede ,  Dominique Savignac ,  Helmut Fischer

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/028 ,  G11C7/1045 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/50 ,  G11C29/50012

Abstract: In the method for modifying a default time duration between an execution instant of a second operation and an earlier execution instant of a first operation executed earlier in a memory element, wherein the memory element is operable in a test operation mode and a normal operation mode, at first a real time duration in the memory element is determined and provided during the test operation mode, wherein the real time duration is chosen so that a performance parameter of the memory element, when using the real time duration between the execution instants of the first and second operations, improves over a situation in which the default time duration between the execution instants of the first and second operations is used. Then, the default time duration is changed in direction of the real time duration during the test operation mode to obtain a modified default time duration. Then information on the modified default time duration or on the ascertained real time duration are stored in the memory element during the test operation mode, wherein the second operation is executed offset by the modified default time duration after the execution instant of the first operation during the normal operation mode.

Abstract translation: 在用于修改第二操作的执行时刻和先前在存储元件中执行的第一操作的较早执行时刻之间的默认持续时间的方法中，其中该存储元件可在测试操作模式和正常操作模式下操作， 首先，在测试操作模式期间确定和提供存储器元件中的实时持续时间，其中选择实时持续时间，使得当使用第一时钟的执行时刻之间的实时持续时间时，存储器元件的性能参数 并且第二操作改进了使用第一操作和第二操作的执行时刻之间的默认持续时间的情况。 然后，在测试操作模式期间，在实时持续时间的方向上改变默认持续时间，以获得修改的默认持续时间。 然后，在测试操作模式期间将关于修改的默认持续时间或所确定的实时持续时间的信息存储在存储器元件中，其中第二操作被执行偏移了在第一操作期间的执行时刻之后的修改的默认持续时间 正常运行模式。

公开(公告)号：US07064999B2

公开(公告)日：2006-06-20

申请号：US10342901

申请日：2003-01-15

Applicant: Helmut Fischer ,  Ullrich Menczigar ,  Johann Pfeiffer

Inventor： Helmut Fischer ,  Ullrich Menczigar ,  Johann Pfeiffer

IPC: G11C8/00

CPC classification number: G11C7/1042 ,  G11C7/1048 ,  G11C2207/002

Abstract: A digital memory circuit has at least two pairs of adjacent memory banks. Each of the banks has n parallel terminals for n read/write data lines. Each bank pair has only two bundles of n/2 read/write data lines. A first bundle is assigned to the first half of a first bank and to a second half of a second bank and the second bundle is assigned to a second half of the first bank and to a first half of the second bank. Data are input/output in parallel to n/2 input/output lines with the timing of successive half-periods of a clock signal. A changeover device is changeable between different switching states for connecting a bundle of n/2 input/output lines to the read/write data lines of the bank pair containing the addressed bank, depending on whether the data are assigned to the first or second half-period of the clock signal.

Abstract translation: 数字存储电路具有至少两对相邻的存储体。 每个存储体具有n个用于n个读/写数据线的并行端子。 每个银行对只有两束n / 2个读/写数据线。 第一束被分配给第一组的前半部分和第二组的第二半部分，并且第二组分配给第一组的后半部分和第二组的第二半部分。 数据与时钟信号的连续半周期的定时与n / 2输入/输出线并联输入/输出。 根据是否将数据分配给第一或第二半部分，可以在不同的切换状态之间改变用于将一束n / 2个输入/输出线连接到包含寻址的存储体的存储体对的读/写数据线的不同切换状态 时钟信号的周期。

公开(公告)号：US06930540B2

公开(公告)日：2005-08-16

申请号：US10460714

申请日：2003-06-12

Applicant: Michael Sommer ,  Helmut Fischer

Inventor： Michael Sommer ,  Helmut Fischer

IPC: G11C5/14 ,  G11C11/4074 ,  G05F3/02

CPC classification number: G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

Abstract: An integrated circuit has a voltage divider that is configured to save current. The circuit includes a capacitor that is inventively connected to a potential sink or potential source by way of a charge branch even when the voltage divider is inactive. The capacitor is thus held at a charge state that corresponds to the charge state given an active voltage divider. The voltage divider thus becomes functional in a shorter time following activation, because the capacitor does not require recharging.

Abstract translation: 集成电路具有配置为节省电流的分压器。 电路包括电容器，即使当分压器不活动时，电容器通过电荷分支发明地连接到电位吸收器或电位源。 因此，电容器保持在对应于给定有源分压器的充电状态的充电状态。 因此，由于电容器不需要充电，因此分压器在激活后的较短时间内变得功能化。

公开(公告)号：US20050141336A1

公开(公告)日：2005-06-30

申请号：US11009557

申请日：2004-12-10

Applicant: Helmut Fischer

Inventor： Helmut Fischer

IPC: G11C5/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4078 ,  G11C29/00 ,  H01L21/00

CPC classification number: G11C7/1045 ,  G11C7/1072 ,  G11C11/4076

Abstract: One embodiment of the invention provides a method for producing an integrated memory module containing a command decoding device that responds to external operation commands to set operating states of the memory module for carrying out operations in accordance with a predetermined specification of the memory module. The command decoding device is formed with a decision memory containing memory locations Mi,j, the storage capacity of which suffices to receive, for an arbitrary specification from a plurality of different specifications, a decision information item specifying whether or how the second operation command of selected pairs of two directly successive operation commands is to be executed. After integration of the command decoding device thus formed, the decision information items demanded in the case of the predetermined specification are written to the memory locations of the decision memory.

Abstract translation: 本发明的一个实施例提供了一种用于产生集成存储器模块的方法，该集成存储器模块包含响应于外部操作命令的命令解码装置，以根据存储器模块的预定规范设置用于执行操作的存储器模块的操作状态。 命令解码装置形成有判定存储器，该判定存储器包含存储器位置M i，j，其存储容量对于来自多个不同规格的任意规范就足以接收指定的决定信息项 是否要执行所选择的两个直接连续操作命令的对的第二操作命令。 在如此形成的命令解码装置的集成之后，将在预定规格的情况下所要求的判定信息项写入决定存储器的存储单元。

公开(公告)号：US06903423B2

公开(公告)日：2005-06-07

申请号：US10843318

申请日：2004-05-12

Applicant: Helmut Fischer ,  Jens Egerer

Inventor： Helmut Fischer ,  Jens Egerer

IPC: G11C5/14 ,  G11C11/407 ,  G11C29/00 ,  G11C29/02 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: G11C29/02 ,  G11C2029/5006

Abstract: An integrated semiconductor memory can include a plurality of subcircuit blocks arranged on nonoverlapping area sections. The subcircuit blocks each have a block supply line and a block ground line, which supply individual switching elements of the subcircuit blocks with a voltage. Each block supply line and block ground line is connected to a chip supply line and a chip ground line, which run outside the area sections of the subcircuit blocks. At least one connection between the chip supply line and the block supply line of at least one subcircuit block or between the chip ground line and the block ground line of at least one subcircuit block can be isolated by a switching device. Furthermore, a method for reducing leakage currents in a semiconductor memory, which, depending on the operating state of the semiconductor memory, isolates or connects individual subcircuit blocks of the semiconductor memory from or to a voltage supply.

Abstract translation: 集成半导体存储器可以包括布置在非重叠区域部分上的多个子电路块。 每个子电路块具有块供电线和块接地线，其为电路中的各个电路块的各个开关元件提供电压。 每个块供电线和块接地线连接到芯片供电线和芯片接地线，其在子电路块的区域外延伸。 至少一个子电路块的芯片供给线和块供应线之间或至少一个子电路块的芯片接地线和块接地线之间的至少一个连接可以由开关器件隔离。 此外，一种减少半导体存储器中漏电流的方法，其取决于半导体存储器的工作状态，将半导体存储器的各个子电路块与电压源隔离或连接。

公开(公告)号：US20050002245A1

公开(公告)日：2005-01-06

申请号：US10850817

申请日：2004-05-21

Applicant: Ruediger Brede ,  Dominique Savignac ,  Helmut Fischer

Inventor： Ruediger Brede ,  Dominique Savignac ,  Helmut Fischer

IPC: G11C7/10 ,  G11C11/4076 ,  G11C29/50 ,  G11C7/00

CPC classification number: G11C29/028 ,  G11C7/1045 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/50 ,  G11C29/50012

Abstract: In the method for modifying a default time duration between an execution instant of a second operation and an earlier execution instant of a first operation executed earlier in a memory element, wherein the memory element is operable in a test operation mode and a normal operation mode, at first a real time duration in the memory element is determined and provided during the test operation mode, wherein the real time duration is chosen so that a performance parameter of the memory element, when using the real time duration between the execution instants of the first and second operations, improves over a situation in which the default time duration between the execution instants of the first and second operations is used. Then, the default time duration is changed in direction of the real time duration during the test operation mode to obtain a modified default time duration. Then information on the modified default time duration or on the ascertained real time duration are stored in the memory element during the test operation mode, wherein the second operation is executed offset by the modified default time duration after the execution instant of the first operation during the normal operation mode.

Abstract translation: 在用于修改第二操作的执行时刻和先前在存储元件中执行的第一操作的较早执行时刻之间的默认持续时间的方法中，其中该存储元件可在测试操作模式和正常操作模式下操作， 首先，在测试操作模式期间确定和提供存储器元件中的实时持续时间，其中选择实时持续时间，使得当使用第一时钟的执行时刻之间的实时持续时间时，存储器元件的性能参数 并且第二操作改进了使用第一操作和第二操作的执行时刻之间的默认持续时间的情况。 然后，在测试操作模式期间，在实时持续时间的方向上改变默认持续时间，以获得修改的默认持续时间。 然后，在测试操作模式期间将关于修改的默认持续时间或所确定的实时持续时间的信息存储在存储器元件中，其中第二操作被执行偏移了在第一操作期间的执行时刻之后的修改的默认持续时间 正常运行模式。