公开(公告)号：US06566194B1

公开(公告)日：2003-05-20

申请号：US09968465

申请日：2001-10-01

申请人： Mark T. Ramsbey ,  Yu Sun ,  Chi Chang

发明人： Mark T. Ramsbey ,  Yu Sun ,  Chi Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11531

摘要： The present invention provides processes for doping and saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, word lines are doped prior to patterning the poly layer from which the word lines are formed in the core region. Thereby, the poly layer protects the substrate between the word lines from doping that could cause shorting between bit lines. According to another aspect of the invention, word lines are exposed while spacer material, dielectric, or like material protects the substrate between word lines. The spacer material or dielectric prevents the substrate from becoming salicided in a manner that, like doping, could cause shorting between bit lines. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines even in virtual ground arrays where there are no oxide island isolation regions between bit lines.

摘要翻译： 本发明提供了在虚拟接地阵列闪速存储器件中掺杂和打字字线的方法，而不引起位线之间的短路。 根据本发明的一个方面，在对在芯区域内形成字线的多层图案进行图案化之前，对字线进行掺杂。 因此，多层保护字线之间的衬底免受可能导致位线之间短路的掺杂。 根据本发明的另一方面，字线被暴露，而隔离材料，电介质或类似材料在字线之间保护衬底。 间隔物材料或电介质防止衬底以像掺杂那样在位线之间引起短路的方式变为水溶液。 本发明提供了具有掺杂和含水字线的虚拟接地阵列闪存器件，但即使在位线之间不存在氧化物岛隔离区域的虚拟接地阵列中也不会在位线之间发生短路。

公开(公告)号：US06420752B1

公开(公告)日：2002-07-16

申请号：US09502163

申请日：2000-02-11

申请人： Minh Van Ngo ,  Yu Sun ,  Fei Wang ,  Mark T. Ramsbey ,  Chi Chang ,  Angela T. Hui ,  Mark S. Chang

发明人： Minh Van Ngo ,  Yu Sun ,  Fei Wang ,  Mark T. Ramsbey ,  Chi Chang ,  Angela T. Hui ,  Mark S. Chang

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/115 ,  H01L2924/3011

摘要： A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.

摘要翻译： 公开了一种用于最小化自动掺杂问题的半导体器件。 蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。 衬垫氧化物层直接形成在衬底上并且与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触并且用作介电层的自动掺杂势垒，以防止形成在衬底中的硼和磷 电介质层自动掺入源和漏极。

公开(公告)号：US06399984B1

公开(公告)日：2002-06-04

申请号：US09882242

申请日：2001-06-15

申请人： Yider Wu ,  Mark T. Ramsbey ,  Chi Chang ,  Yu Sun ,  Tuan Duc Pham ,  Jean Y. Yang

发明人： Yider Wu ,  Mark T. Ramsbey ,  Chi Chang ,  Yu Sun ,  Tuan Duc Pham ,  Jean Y. Yang

IPC分类号： H01L29788

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A predetermined species such as nitrogen is placed at an interface between a bit line junction and a dielectric layer of a control dielectric structure of a flash memory device to minimize degradation of such an interface by minimizing formation of interface defects during program or erase operations of the flash memory device. The predetermined species such as nitrogen is implanted into a bit line junction of the flash memory device. A thermal process is performed that heats up the semiconductor wafer such that the predetermined species such as nitrogen implanted within the semiconductor wafer thermally drifts to the interface between the bit line junction and the control dielectric structure during the thermal process. The predetermined species such as nitrogen at the interface minimizes formation of interface defects and thus degradation of the interface with time during the program or erase operations of the flash memory device.

摘要翻译： 将诸如氮的预定物质放置在闪存存储器件的控制电介质结构的位线结和电介质层之间的界面处，以通过在编程或擦除操作期间最小化界面缺陷的形成来最小化这种界面的劣化 闪存设备。 将诸如氮的预定物质注入到闪速存储器件的位线结中。 执行加热半导体晶片的热处理，使得在热处理期间注入到半导体晶片内的预定物质例如氮漂移到位线结和控制电介质结构之间的界面。 在闪存器件的编程或擦除操作期间，预定种类例如接口处的氮使界面缺陷的形成最小化，从而使界面的时效性降低。

公开(公告)号：US06133619A

公开(公告)日：2000-10-17

申请号：US144521

申请日：1998-08-31

申请人： Kashmir Sahota ,  Richard J. Huang ,  David Matsumoto ,  Mark T. Ramsbey ,  Yu Sun ,  Judith Quan Rizzuto

发明人： Kashmir Sahota ,  Richard J. Huang ,  David Matsumoto ,  Mark T. Ramsbey ,  Yu Sun ,  Judith Quan Rizzuto

IPC分类号： H01L21/312 ,  H01L21/314 ,  H01L21/768 ,  H01L51/00

CPC分类号： H01L21/76801 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/3124 ,  H01L21/3145

摘要： Outgassing from a dielectric gap fill layer, e.g., a low dielectric constant material such as HSQ, and attendant deformation or delamination of a barrier dielectric layer on an overlying patterned conductive layer during subsequent thermal processing are avoided or significantly reduced by controlling the thickness of the dielectric cap layer on the dielectric gap fill layer. Embodiments include depositing a conformal SiON barrier on a first conductive pattern, depositing a HSQ gap fill layer on the conformal SiON barrier layer, depositing a silicon oxide cap layer and planarizing such that the thickness of the planarized silicon cap layer is at least 2500 .ANG., thereby avoiding deformation and/or delamination of a conformal SiON barrier layer on an overlying patterned conductive layer during subsequent thermal processing.

摘要翻译： 从介电间隙填充层，例如低介电常数材料（例如HSQ）以及随后的热处理过程中覆盖的图案化导电层上的阻挡介电层的伴随变形或分层的脱气被避免或显着减少，通过控制 电介质间隙填充层上的介电覆盖层。 实施例包括在第一导电图案上沉积保形SiON阻挡层，在保形SiON阻挡层上沉积HSQ间隙填充层，沉积氧化硅覆盖层并进行平坦化，使得平坦化硅覆盖层的厚度为至少2500， 从而避免在随后的热处理期间覆盖的图案化导电层上的保形SiON阻挡层的变形和/或分层。

公开(公告)号：US06040597A

公开(公告)日：2000-03-21

申请号：US23166

申请日：1998-02-13

申请人： Unsoon Kim ,  Yowjuang W. Liu ,  Yu Sun

发明人： Unsoon Kim ,  Yowjuang W. Liu ,  Yu Sun

IPC分类号： H01L21/762 ,  H01L29/788

CPC分类号： H01L21/76232 ,  H01L21/76237

摘要： A wet etching process for establishing isolation grooves in a flash memory core wafer includes depositing nitride and/or oxide layers on a silicon substrate of the wafer, depositing a photoresist layer thereon, and then exposing predetermined portions of the photoresist layer to ultraviolet light to establish a desired groove pattern in the photoresist layer. A dry etching process is then used to remove the nitride and/or oxide layers beneath the groove pattern of the photoresist layer to thereby expose portions of the substrate. Next, the wafer is disposed in a wet etching solution such as potassium hydroxide to form grooves in the exposed portions of the silicon substrate. The wafer is oriented and disposed in the bath as appropriate for forming V-shaped grooves, such that after etching, the angled walls of the grooves can be easily exposed to a dopant beam directly above the wafer, without having to tilt the wafer or beam source. Thereby, the walls of the grooves are easily implanted with dopant.

摘要翻译： 用于在闪速存储器芯晶片中建立隔离槽的湿蚀刻工艺包括在晶片的硅衬底上沉积氮化物和/或氧化物层，在其上沉积光致抗蚀剂层，然后将光致抗蚀剂层的预定部分暴露于紫外光以建立 在光致抗蚀剂层中的期望的凹槽图案。 然后使用干蚀刻工艺去除光致抗蚀剂层的凹槽图案下方的氮化物和/或氧化物层，从而暴露衬底的部分。 接下来，将晶片设置在诸如氢氧化钾的湿蚀刻溶液中，以在硅衬底的暴露部分中形成凹槽。 晶片被定向并适当地设置在浴中以形成V形槽，使得在蚀刻之后，槽的成角度的壁可以容易地暴露于直接在晶片上方的掺杂剂束，而不必使晶片或光束倾斜 资源。 因此，槽的壁容易用掺杂剂注入。

公开(公告)号：US6002151A

公开(公告)日：1999-12-14

申请号：US993890

申请日：1997-12-18

申请人： Yowjuang William Liu ,  Yu Sun ,  Donald L. Wollesen

发明人： Yowjuang William Liu ,  Yu Sun ,  Donald L. Wollesen

IPC分类号： H01L21/8247 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76 ,  H01L29/88 ,  H01L29/92

CPC分类号： H01L27/11521 ,  H01L29/42336 ,  H01L29/7883

摘要： A non-volatile memory device is formed in a substrate, thereby enabling increased densification. Embodiments include forming a trench in a substrate, forming a substantially U-shaped tunnel dielectric layer in the trench, depositing a substantially U-shaped floating gate electrode on the tunnel dielectric layer, forming a dielectric layer on the floating gate electrode extending on the substrate surface and forming a substantially T-shaped control gate electrode filling the trench and extending on the substrate. Sidewall spacers are formed on side surfaces of the control gate electrode and dielectric layer, followed by ion implantation to form source/drain regions extending into the substrate to substantially the same depth, leaving a region containing an impurity of the first conductivity type at the intersection of the trench and substrate surface which prevents shorting between the source/drain region and gate electrodes.

摘要翻译： 在基板中形成非易失性存储器件，从而能够增加致密化。 实施例包括在衬底中形成沟槽，在沟槽中形成基本为U形的隧道介电层，在隧道介电层上沉积基本为U形的浮动栅电极，在衬底上延伸的浮栅上形成电介质层 并且形成填充沟槽并在衬底上延伸的基本上T形的控制栅电极。 侧壁间隔物形成在控制栅电极和电介质层的侧表面上，然后进行离子注入，以形成延伸到衬底中的基本相同深度的源极/漏极区域，在相交处留下含有第一导电类型杂质的区域 的沟槽和衬底表面，防止源极/漏极区域和栅电极之间的短路。

公开(公告)号：US5470773A

公开(公告)日：1995-11-28

申请号：US233174

申请日：1994-04-25

申请人： David K. Y. Liu ,  Yu Sun ,  Chi Chang

发明人： David K. Y. Liu ,  Yu Sun ,  Chi Chang

IPC分类号： H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/11536

摘要： A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.

摘要翻译： 公开了一种用于保护半导体器件的堆叠栅极边缘的工艺。 该方法提供在完成自对准源（SAS）蚀刻之前提供间隔物形成。 通过在SAS蚀刻之前提供间隔物形成，隧道氧化物完整性得到很大改善，并且源极结注入轮廓更均匀，因为源区周围的硅不会被去除。

公开(公告)号：US10708673B2

公开(公告)日：2020-07-07

申请号：US15758881

申请日：2015-09-25

申请人： QUALCOMM Incorporated ,  Ning Bi ,  Fan Ling ,  Jingting Ding ,  Yu Sun

发明人： Ning Bi ,  Fan Ling ,  Jingting Ding ,  Yu Sun

IPC分类号： H04N21/845 ,  G06F16/71 ,  G06F16/738 ,  G06F16/74 ,  H04N21/8549 ,  H04N21/234 ,  H04N21/2343 ,  H04N21/81 ,  H04N21/2187 ,  G06F16/783 ,  H04N21/4725 ,  H04N7/18 ,  G06K9/00 ,  H04N21/472

摘要： A system and method of video processing are disclosed. In a particular implementation, a device includes a processor configured to generate index data for video content. The index data includes a summary frame and metadata. The summary frame is associated with a portion of the video content and illustrates multiple representations of an object included in the portion of the video content. The metadata includes marker data that indicates a playback position of the video content. The playback position is associated with the summary frame. The device also includes a memory configured to store the index data.

公开(公告)号：US10572802B1

公开(公告)日：2020-02-25

申请号：US16236715

申请日：2018-12-31

申请人： Yu Sun ,  Troi Williams

发明人： Yu Sun ,  Troi Williams

IPC分类号： G06N3/04 ,  G06N3/08 ,  G06N7/00

摘要： A noise and bias can be determined for a sensor. An input vector can be received. A parameter vector can be generated based at least in part on a feed-forward neural network. Components can be determined using the parameter vector based at least in part on a mixture model. A conditional probability density function can be generated based at least in part on the conditional probability density function.

公开(公告)号：US09764469B1

公开(公告)日：2017-09-19

申请号：US14568755

申请日：2014-12-12

申请人： Yu Sun ,  Yuongqiang Huang

发明人： Yu Sun ,  Yuongqiang Huang

IPC分类号： G05B19/18 ,  B25J9/16

CPC分类号： B25J9/1664 ,  G05B2219/36422 ,  G05B2219/40391 ,  G05B2219/40431

摘要： Aspects of the generation of new robotic motion trajectories are described. In one embodiment, a new robot motion trajectory may be generated by gathering demonstrated motion trajectories, adapting the demonstrated motion trajectories into robot-reachable motion trajectories based on a joint space of a robot model, for example, and generating motion harmonics with reference to the motion trajectories. Further, one or more constraints may be specified for a new goal. The weights of the motion harmonics may then be searched to identify or generate a new motion trajectory for a robot, where the new motion minimizes discrepancy from the demonstrated motion trajectories and error due to the at least one constraint. In the new motion trajectory, the degree to which the constraints are satisfied may be tuned using a weight. According to the embodiments, new motion variants may be generated without the need to learn or review new demonstrated trajectories.