公开(公告)号：US08883655B2

公开(公告)日：2014-11-11

申请号：US13897050

申请日：2013-05-17

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik

IPC: H01L21/31 ,  H01L21/469 ,  H01L45/00 ,  H01L21/02 ,  C23C16/455 ,  C23C16/40 ,  H01L27/24

CPC classification number: H01L45/145 ,  C23C16/40 ,  C23C16/45525 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/0228 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.

Abstract translation: 本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。 金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。 设置在金属氧化物层之间的界面有助于氧空位移动。 在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对齐的晶粒界面，其包含平行于电极界面延伸的许多晶界。 因此，氧空缺在切换期间被捕获和释放，而空位明显损失。 因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

公开(公告)号：US08871564B2

公开(公告)日：2014-10-28

申请号：US14194082

申请日：2014-02-28

Applicant: Intermolecular Inc.

Inventor： Yun Wang ,  Imran Hashim

IPC: H01L29/02 ,  H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625

Abstract: Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.

公开(公告)号：US20140315369A1

公开(公告)日：2014-10-23

申请号：US14317155

申请日：2014-06-27

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/56 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.

Abstract translation: 提供了诸如电阻随机存取存储器（ReRAM）单元的半导体器件，其包括由过渡金属的合金形成的限流层。 这种合金的一些实例包括还可以包括镍，铝和/或硅的含铬合金。 其它实例包括也可以包括硅和碳的组合或铝和氮的组合的含钽和/或钛的合金。 这些限流层可具有至少约1欧姆 - 厘米的电阻率。 即使当这些层受到强电场和/或高温处理时，也保持该电阻率水平。 在一些实施例中，限流层的击穿电压为至少约8V。 层的高电阻率允许在保持其性能的同时缩小包括这些层的半导体器件的尺寸。

公开(公告)号：US20140264252A1

公开(公告)日：2014-09-18

申请号：US14294519

申请日：2014-06-03

Applicant: Intermolecular, Inc.

Inventor： Imran Hashim ,  Venkat Ananthan ,  Tony P. Chiang ,  Prashant B. Phatak

IPC: H01L27/24 ,  H01L29/872

CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L29/872 ,  H01L45/10

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

Abstract translation: 可适用于存储器件应用的选择器器件可在低电压下具有低漏电流，以减少非选定器件的漏电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 在一些实施例中，选择器装置可以包括第一电极，三层电介质层和第二电极。 三层电介质层可以包括夹在两个较低的漏电介质层之间的高泄漏电介质层。 低泄漏层可以起到限制低电压下选择器装置的电流的作用。 高泄漏电介质层可以用于在高电压下增强选择器装置上的电流。

公开(公告)号：US20140224645A1

公开(公告)日：2014-08-14

申请号：US14254155

申请日：2014-04-16

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Hieu Pham ,  Vidyut Gopal ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Yun Wang ,  Takeshi Yamaguchi ,  Hong Sheng Yang

IPC: H01L45/00

CPC classification number: C23C14/345 ,  C23C14/0042 ,  C23C14/0641 ,  C23C14/083 ,  C23C14/225 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625

Abstract: A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 Ωcm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.

Abstract translation: 公开了一种非易失性存储元件，其包括第一电极，具有双稳态电阻的近化学计量的金属氧化物存储层和与近化学计量的金属氧化物存储层接触的第二电极。 至少一个电极是包含亚化学计量的过渡金属氮化物或氧氮化物的电阻电极，并且电阻率在0.1和10Ω之间。 电阻电极提供嵌入式限流电阻器的功能，并且还用作用于设置和复位金属氧化物层的电阻状态的氧空位的源极和吸收器。 还公开了用于第二电极的新颖制造方法。

公开(公告)号：US20140192585A1

公开(公告)日：2014-07-10

申请号：US13738061

申请日：2013-01-10

Applicant: INTERMOLECULAR INC. ,  KABUSHIKI KAISHA TOSHIBA ,  SANDISK 3D LLC

Inventor： Imran Hashim ,  Ryan C. Clarke ,  Nan Lu ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: G11C13/00 ,  H01L45/00

CPC classification number: H01L45/146 ,  G11C11/56 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253

Abstract: Provided are resistive random access memory (ReRAM) cells, each having three or more resistive states and being capable of storing multiple bits of data, as well as methods of fabricating and operating such ReRAM cells. Such ReRAM cells or, more specifically, their resistive switching layer have wide range of resistive states and are capable of being very conductive (e.g., about 1 kOhm) in one state and very resistive (e.g., about 1 MOhm) in another state. In some embodiments, a resistance ratio between resistive states may be between 10 and 1,000 even up to 10,000. The resistive switching layers also allow establishing stable and distinct intermediate resistive states that may be assigned different data values. These layers may be configured to switching between their resistive states using fewer programming pulses than conventional systems by using specific materials, switching pluses, and resistive state threshold.

Abstract translation: 提供了电阻随机存取存储器（ReRAM）单元，每个单元具有三个或更多个电阻状态，并且能够存储多个数据位，以及制造和操作这样的ReRAM单元的方法。 这样的ReRAM单元或更具体地，它们的电阻式开关层具有宽范围的电阻状态，并且在另一状态下能够在一种状态下非常导电（例如，约1kOhm），并且在另一状态下具有很强的电阻（例如约1MOhm）。 在一些实施例中，电阻状态之间的电阻比可以在10和1,000之间甚至高达10,000。 电阻式开关层还允许建立可分配不同数据值的稳定和不同的中间电阻状态。 这些层可以被配置为使用比常规系统更少的编程脉冲在其电阻状态之间切换，通过使用特定的材料，开关和电阻状态阈值。

公开(公告)号：US20140175360A1

公开(公告)日：2014-06-26

申请号：US13721358

申请日：2012-12-20

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Mihir Tendulkar ,  Vidyut Gopal ,  Imran Hashim ,  Randall J. Higuchi ,  Tim Minvielle ,  Yun Wang ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1625

Abstract: Provided are resistive random access memory (ReRAM) cells having bi-layered metal oxide structures. The layers of a bi-layered structure may have different compositions and thicknesses. Specifically, one layer may be thinner than the other layer, sometimes as much as 5 to 20 times thinner. The thinner layer may be less than 30 Angstroms thick or even less than 10 Angstroms thick. The thinner layer is generally more oxygen rich than the thicker layer. Oxygen deficiency of the thinner layer may be less than 5 atomic percent or even less than 2 atomic percent. In some embodiments, a highest oxidation state metal oxide may be used to form a thinner layer. The thinner layer typically directly interfaces with one of the electrodes, such as an electrode made from doped polysilicon. Combining these specifically configured layers into the bi-layered structure allows improving forming and operating characteristics of ReRAM cells.

Abstract translation: 提供了具有双层金属氧化物结构的电阻随机存取存储器（ReRAM）单元。 双层结构的层可以具有不同的组成和厚度。 具体地说，一层可以比另一层薄一些，有时可以减薄5至20倍。 较薄的层可以小于30埃厚或甚至小于10埃厚。 较薄的层通常比较厚的层富氧。 较薄层的缺氧可能小于5原子％或甚至小于2原子％。 在一些实施方案中，可以使用最高氧化态金属氧化物来形成较薄的层。 较薄的层通常直接与一个电极（例如由掺杂多晶硅制成的电极）接合。 将这些特定配置的层组合成双层结构允许改善ReRAM单元的成形和操作特性。

公开(公告)号：US20140154859A1

公开(公告)日：2014-06-05

申请号：US13705516

申请日：2012-12-05

Applicant: INTERMOLECULAR INC.

Inventor： Vidyut Gopal ,  Tony P. Chiang ,  Imran Hashim ,  Randall J. Higuchi ,  Robert A. Huertas ,  Hieu Pham ,  Yun Wang

IPC: H01L49/02

CPC classification number: H01L22/34 ,  H01L45/08 ,  H01L45/145

Abstract: Provided are methods for processing different materials on the same substrate for high throughput screening of multiple ReRAM materials. A substrate may be divided into multiple site isolated regions, each region including one or more base structures operable as bottom electrodes of ReRAM cells. Different test samples may be formed over these base structures in a combinatorial manner. Specifically, each site isolated region may receive a test sample that has a different characteristic than at least one other sample provided in another region. The test samples may have different compositions and/or thicknesses or be deposited using different techniques. These different samples are then etched in the same operation to form portions of the samples. Each portion is substantially larger than the corresponding base structure and fully covers this base structure to protect the interface between the base structure and the portion during etching.

Abstract translation: 提供了在同一基板上处理不同材料的方法，用于多个ReRAM材料的高通量筛选。 衬底可以被分成多个位置隔离区域，每个区域包括可操作为ReRAM单元的底部电极的一个或多个基底结构。 可以以组合的方式在这些基础结构上形成不同的测试样品。 具体地说，每个位置隔离区域可以接收具有与另一区域中提供的至少一个其他样品不同的特性的测试样品。 测试样品可以具有不同的组成和/或厚度或使用不同的技术沉积。 然后在相同的操作中蚀刻这些不同的样品以形成样品的一部分。 每个部分基本上大于对应的基部结构，并且完全覆盖该基部结构以在蚀刻期间保护基部结构和该部分之间的界面。

公开(公告)号：US20140134794A1

公开(公告)日：2014-05-15

申请号：US14156762

申请日：2014-01-16

Applicant: Intermolecular Inc. ,  SanDisk 3D LLC ,  Kabushiki Kaisha Toshiba

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/065 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract translation: 本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。 通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。 在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成 器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

公开(公告)号：US08704203B2

公开(公告)日：2014-04-22

申请号：US13971467

申请日：2013-08-20

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Hieu Pham ,  Vidyut Gopal ,  Imran Hashim ,  Tim Minvielle ,  Yun Wang ,  Takeshi Yamaguchi ,  Hong Sheng Yang

IPC: H01L29/02

CPC classification number: H01L45/08 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 Å and about 100 Å, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

Abstract translation: 本发明的实施例包括非易失性存储器元件和包括非易失性存储元件的存储器件。 还公开了形成非易失性存储元件的方法。 非易失性存储元件包括第一电极层，第二电极层和设置在第一和第二电极层之间的多个氧化物层。 氧化物层中的一个具有线性电阻和亚化学计量组成，另一个氧化物层具有双稳态电阻和近化学计量组成。 优选地，两个氧化物层厚度的总和在约和之间，并且具有双稳态电阻的氧化物层具有在总厚度的约25％至约75％之间的厚度。 在一个实施例中，氧化物层在具有受控的氩气和氧气的气氛中使用反应溅射形成。