公开(公告)号：US11552403B2

公开(公告)日：2023-01-10

申请号：US17512504

申请日：2021-10-27

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Min Suet Lim ,  Boon Ping Koh ,  Wil Choon Song ,  Khang Choong Yong

IPC分类号： H01Q13/18 ,  H01Q1/38 ,  H01Q21/28

摘要： Embodiments herein disclose techniques for apparatuses and methods for making a slot antenna on a PCB with a cutout. A PCB may include a metal layer. The metal layer may include a cavity to be a first radiating element of an antenna, and a slot to be a second radiating element of the antenna. In addition, the cavity may extend to be the cutout of the PCB through other layers of the PCB. The first and second radiating elements may provide a determined transmission frequency for the antenna. The metal layer may further include a portion of a transmission line of the antenna, and the transmission line is in contact with the cavity and the slot. A package may be affixed to the PCB, where a portion of the package may be within the cutout of the PCB. Other embodiments may be described and/or claimed.

公开(公告)号：US11264315B2

公开(公告)日：2022-03-01

申请号：US15845531

申请日：2017-12-18

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir ,  Hoay Tien Teoh ,  Jimmy Huat Since Huang

IPC分类号： H01L23/498 ,  H05K1/18 ,  H01L21/56 ,  H01L23/522 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H05K3/34

摘要： An electronic package with passive components located between a first substrate and a second substrate. The electronic package can include a first substrate including a device interface for communication with an electronic device. An interposer can be electrically coupled to the first substrate. A second substrate can be offset from the first substrate at a distance. The second substrate can be electrically coupled to the first substrate through the interposer. A passive component can be attached to one of the first substrate or the second substrate. The passive component can be located between the first substrate and the second substrate. A height of the passive component can be is less than the distance between the first substrate and the second substrate. The second substrate can include a die interface configured for communication with a die. The die interface can be communicatively coupled to the passive component.

公开(公告)号：US11178768B2

公开(公告)日：2021-11-16

申请号：US15089303

申请日：2016-04-01

申请人： Intel Corporation

发明人： Khang Choong Yong ,  Stephen H. Hall ,  Tin Poay Chuah ,  Boon Ping Koh ,  Eng Huat Goh

IPC分类号： H05K1/18 ,  H05K1/14 ,  H01L25/18 ,  G06K9/00 ,  H05K1/02 ,  H05K9/00 ,  H05K3/36

摘要： Three-dimensional (3-D) volumetric board architectural design provides technical solutions to technical problems facing miniaturization of circuit boards. The 3-D volumetric architecture includes using more of the unused volume in the vertical dimension (e.g., Z-dimension) to increase the utilization of the total circuit board volume. The 3-D volumetric architecture is realized by mounting components on a first PCB and on a second PCB, and inverting and suspending the second PCB above the first PCB. The use of 3-D volumetric board architectural design further enables formation of a shielded FEMIE, providing shielding and improved volumetric use with little or no reduction in system performance or increase in system Z-height.

公开(公告)号：US11177226B2

公开(公告)日：2021-11-16

申请号：US16450266

申请日：2019-06-24

申请人： Intel Corporation

发明人： Bok Eng Cheah ,  Eng Huat Goh ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim

IPC分类号： H01L23/60 ,  H01L23/48 ,  H01L25/07 ,  H01L25/11 ,  H01L25/065

摘要： An electronic device and associated methods are disclosed. In one example, the electronic device includes a first device and a second device coupled to a surface of a substrate, and a continuous flexible shield woven over the first device and under the second device to separate the first device from the second device. In selected examples, the continuous flexible shield may be formed from a laminate and one or more of the devices may be coupled through an opening or via in the continuous flexible shield.

公开(公告)号：US11133261B2

公开(公告)日：2021-09-28

申请号：US15845336

申请日：2017-12-18

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Min Suet Lim ,  Chee Kheong Yoon ,  Jia Yan Go

IPC分类号： H01L23/538 ,  H01L25/10 ,  H05K1/18 ,  H01L25/00 ,  H01L25/18 ,  H01L23/18 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31

摘要： An electronic device may be a first package. The first package may include a first substrate having a first mounting surface. A first die may be coupled to the first mounting surface. A first interconnect region may be laterally spaced from the first die. The first package may be interconnected with a second package. The second package may include a second die coupled to a second mounting surface. Interconnection of the first package with the second package may establish one or more electrical communication pathways between the first package and the second package. The interconnection of the first package with the second package may interconnect the first die with the second die such that the first die and second die are in communication only through the one or more electrical communication pathways.

公开(公告)号：US20190364702A1

公开(公告)日：2019-11-28

申请号：US16535766

申请日：2019-08-08

申请人： Intel Corporation

发明人： Min Suet Lim ,  Yew San Lim ,  Jia Yan Go ,  Tin Poay Chuah ,  Eng Huat Goh

IPC分类号： H05K9/00 ,  H05K1/11 ,  H05K3/46

摘要： Apparatus and method for providing an electromagnetic interference (EMI) shield for removable engagement with a printed circuit board (PCB). A shaped electrically conductive member has a substantially planar member portion with multiple lateral member edges. The sidewalls are disposed at respective lateral member edges and are substantially orthogonal to the substantially planar member portion. At least one of the sidewalls includes at least one first snap-fit latching feature to engage a respective complementary second snap-fit latching feature disposed at one or more of multiple peripheral portions of a PCB.

公开(公告)号：US20190342996A1

公开(公告)日：2019-11-07

申请号：US16513004

申请日：2019-07-16

申请人： Intel Corporation

发明人： Chee Ling Wong ,  Wil Choon Song ,  Khang Choong Yong ,  Eng Huat Goh ,  Mohd Muhaiyiddin Bin Abdullah ,  Tin Poay Chuah

IPC分类号： H05K1/11 ,  H05K1/14

摘要： A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

公开(公告)号：US20190306978A1

公开(公告)日：2019-10-03

申请号：US16263370

申请日：2019-01-31

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Hoay Tien Teoh

IPC分类号： H05K1/11 ,  H05K1/02 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

摘要： A jumper may be adapted to transmit an electrical signal. The jumper may be included in a system on a chip. The system on a chip may include a substrate, and the substrate may include one or more routing layers. The jumper may be included in the one or more routing layers of the substrate. A first interconnect may be positioned on a first side of the system on a chip, and a second interconnect may be positioned on a second side of the system on a chip. The jumper may be in electrical communication with the first interconnect, and may be in electrical communication with the second interconnect. The jumper may be electrically isolated from other components of the system on a chip, such as one or more die coupled to the substrate.

公开(公告)号：US20190304914A1

公开(公告)日：2019-10-03

申请号：US16284218

申请日：2019-02-25

申请人： Intel Corporation

发明人： Boon Ping Koh ,  Eng Huat Goh ,  Jiun Hann Sir ,  Khang Choong Yong ,  Min Suet Lim ,  Wil Choon Song

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498

摘要： A semiconductor apparatus includes a floating-bridge interconnect that couples two semiconductive devices that are arranged across a middle semiconductive device. The floating-bridge interconnect can be semiconductive material such as a silicon bridge, or it can be an organic bridge. Computing functions required in one of the two semiconductive devices can be off-loaded to any of the floating-bridge interconnect or the other of the two semiconductive devices.

公开(公告)号：US20190287872A1

公开(公告)日：2019-09-19

申请号：US15925429

申请日：2018-03-19

申请人： INTEL CORPORATION

发明人： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Richard C. Stamey ,  Chu Aun Lim ,  Jimin Yao

IPC分类号： H01L23/31 ,  H01L23/528 ,  H01L23/538 ,  H01L23/00

摘要： A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.