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    Semiconductor memory device and method for production of the semiconductor memory device
    91.
    发明申请
    Semiconductor memory device and method for production of the semiconductor memory device 审中-公开
    半导体存储器件及半导体存储器件的制造方法

    公开(公告)号：US20070257293A1

    公开(公告)日：2007-11-08

    申请号：US11429929

    申请日：2006-05-08

    申请人： Josef Willer

    发明人： Josef Willer

    IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

    CPC分类号： H01L29/42352 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117

    摘要： The semiconductor memory device has a substrate with a main surface, on which parallel trenches are arranged. A memory layer is disposed at the sidewalls of the trenches, and gate electrodes are disposed in the trenches. Buried bitlines are formed as doped regions between neighboring trenches. The buried bitlines abut the sidewalls of the trenches and comprise upper surfaces, which are arranged at a specified distance from the bottom of the trenches. Source/drain regions are formed by sections of the buried bitlines.

    摘要翻译： 半导体存储器件具有主表面的衬底，平行的沟槽布置在其上。 存储层设置在沟槽的侧壁处，栅电极设置在沟槽中。 埋置的位线形成为相邻沟槽之间的掺杂区域。 埋置的位线邻接沟槽的侧壁并且包括上表面，其布置在距离沟槽的底部指定的距离处。 源极/漏极区域由掩埋位线的部分形成。

    Integrated memory device and method for operating the same
    92.
    发明授权
    Integrated memory device and method for operating the same 有权
    集成存储器件及其操作方法

    公开(公告)号：US07280392B2

    公开(公告)日：2007-10-09

    申请号：US11339846

    申请日：2006-01-26

    申请人： Corvin Liaw ,  Josef Willer

    发明人： Corvin Liaw ,  Josef Willer

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0011 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2213/77 ,  H01L27/101

    摘要： A memory device includes an array of memory cells that include a memory element having a non-reactive resistance whose magnitude is programmable to assume a high-resistance state or a low-resistance state. Sets of first and second lines provide access to the memory cells, wherein the memory element of each memory cell is coupled between one of the first lines and one of the second lines. A checking unit determines whether to invert data values to be stored in memory cells coupled to at least a section of respective ones of the first lines based on a number of memory cells that would be programmed in the high-resistance state or the low-resistance state as a result of the data values in order to reduce the number memory cells programmed in the low-resistance state and the resulting leakage current.

    摘要翻译： 存储器件包括存储器单元阵列，其包括具有非反应电阻的存储元件，其大小可编程为呈现高电阻状态或低电阻状态。 第一和第二行的集合提供对存储器单元的访问，其中每个存储器单元的存储元件耦合在第一行之一和第二行中的一个之间。 检查单元基于将以高电阻状态编程的存储器单元的数量或低电阻来确定是否反转要存储在耦合到第一行中的相应的第一行的至少一部分的存储器单元中的数据值 作为数据值的结果，为了减少在低电阻状态下编程的存储单元数量和所产生的漏电流。

    Semiconductor memory device comprising memory cells with floating gate electrode and method of production
    93.
    发明授权
    Semiconductor memory device comprising memory cells with floating gate electrode and method of production 有权
    半导体存储器件包括具有浮栅电极的存储单元和制造方法

    公开(公告)号：US07250651B2

    公开(公告)日：2007-07-31

    申请号：US10921766

    申请日：2004-08-19

    申请人： Karl-Heinz Küsters ,  Josef Willer ,  Corvin Liaw

    发明人： Karl-Heinz Küsters ,  Josef Willer ,  Corvin Liaw

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/062

    CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/792

    摘要： Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the semiconductor material by a tunnel dielectric having essentially the same tiny thickness throughout a primary tunnel area encompassing the area of curvature. The floating gate electrode may bridge the transistor body and is covered with a coupling dielectric provided for a control gate electrode, which forms part of a wordline.

    摘要翻译： 位于浅沟槽隔离物之间的半导体衬底的主表面处的半导体材料的晶体管本体具有圆形或弯曲的上表面。 浮栅电极布置在所述上​​表面之上并且通过隧道电介质与半导体材料电绝缘，所述隧道电介质具有贯穿所述曲率区域的主隧道区域具有基本上相同的微小厚度。 浮栅电极可以桥接晶体管本体，并被形成为形成字线一部分的控制栅电极的耦合电介质覆盖。

    Memory cell with nanocrystals or nanodots
    94.
    发明授权
    Memory cell with nanocrystals or nanodots 有权
    具有纳米晶体或纳米点的记忆体

    公开(公告)号：US07119395B2

    公开(公告)日：2006-10-10

    申请号：US10916013

    申请日：2004-08-11

    申请人： Martin Gutsche ,  Josef Willer ,  Cay-Uwe Pinnow ,  Ralf Symanczyk

    发明人： Martin Gutsche ,  Josef Willer ,  Cay-Uwe Pinnow ,  Ralf Symanczyk

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42332

    摘要： The storage layer (6) is in each case present above a region in which the channel region (3) adjoins a source/drain region (2) and is in each case interrupted above an intervening middle part of the channel region (3). The storage layer (6) is formed by material of the gate dielectric (4) and contains silicon or germanium nanocrystals or nanodots introduced through ion implantation. The gate electrode (5) is widened at the flanks by electrically conductive spacers (7).

    摘要翻译： 存储层（6）在每种情况下都存在于沟道区域（3）邻接源极/漏极区域（2）的区域上方，并且在每个情况下都被中断在沟道区域（3）的中间部分之上。 存储层（6）由栅极电介质（4）的材料形成，并且包含通过离子注入引入的硅或锗纳米晶体或纳米点。 栅电极（5）通过导电间隔物（7）在侧面加宽。

    Flash memory cell, flash memory device and manufacturing method thereof
    95.
    发明授权
    Flash memory cell, flash memory device and manufacturing method thereof 有权
    闪存单元，闪存设备及其制造方法

    公开(公告)号：US07087950B2

    公开(公告)日：2006-08-08

    申请号：US10835390

    申请日：2004-04-30

    申请人： Josef Willer ,  Frank Lau

    发明人： Josef Willer ,  Frank Lau

    IPC分类号： H01L29/76 ,  H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/78645

    摘要： The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source-/drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said channel region; a tunneling dielectric layer formed on the surface of said active region; a floating gate formed on the surface of said tunneling dielectric layer for storing electric charges; an inter-gates coupling dielectric layer formed on the surface of said floating gate, and a control gate formed on the surface of said inter-gates coupling dielectric layer, wherein said floating gate is formed to have a groove-like shape for at least partly encompassing said projecting portion of said active region. This invention further relates to a flash memory device comprising such flash memory cells, as well as a manufacturing method thereof.

    摘要翻译： 本发明涉及一种闪存单元，其包括具有包括沟道区和源 - 漏区的有源区的硅衬底，所述有源区包括突出部分，所述突出部分至少包括所述沟道区; 形成在所述有源区的表面上的隧道电介质层; 形成在用于存储电荷的所述隧道介电层的表面上的浮动栅极; 形成在所述浮置栅极的表面上的栅极间耦合电介质层和形成在所述栅极间耦合电介质层的表面上的控制栅极，其中所述浮动栅极形成为具有至少部分地具有沟槽形状 包围所述有源区域的所述突出部分。 本发明还涉及一种包括这种闪存单元的闪速存储器件及其制造方法。

    Method for producing semiconductor memory devices and integrated memory device
    96.
    发明申请
    Method for producing semiconductor memory devices and integrated memory device 有权
    用于制造半导体存储器件和集成存储器件的方法

    公开(公告)号：US20060145227A1

    公开(公告)日：2006-07-06

    申请号：US11371743

    申请日：2006-03-09

    申请人： Josef Willer

    发明人： Josef Willer

    IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

    CPC分类号： H01L27/105 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573

    摘要： The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local interconnects, which enables to avoid nitride insulations of wordline stacks and to produce CMOS devices of different structures and dimensions in standard technology along with the tinier memory cell transistors.

    摘要翻译： 本发明提供了一种用于存储单元阵列，特别是电荷捕获存储单元阵列的集成方案，其包括局部互连的架构，其能够避免字线堆叠的氮化物绝缘并且在标准技术中产生不同结构和尺寸的CMOS器件 以及更高级的存储单元晶体管。

    Semiconductor memory having charge trapping memory cells and fabrication method
    98.
    发明申请
    Semiconductor memory having charge trapping memory cells and fabrication method 有权
    具有电荷捕获存储单元的半导体存储器和制造方法

    公开(公告)号：US20050286296A1

    公开(公告)日：2005-12-29

    申请号：US11145541

    申请日：2005-06-03

    申请人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    发明人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    IPC分类号： H01L21/8246 ,  H01L27/115 ,  G11C11/34

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

    摘要翻译： 在具有NROM单元的半导体存储器的情况下，存储晶体管的沟道区域在每种情况下相对于相关字线横向延伸，位线布置在字线的顶侧并且以电绝缘的方式 并且存在导电交叉连接，这些交叉连接被布置在字线之间的间隔中并且以与后者的电绝缘的方式布置，并且在下一个序列中在每种情况下连接到位线。

    Memory cell array comprising individually addressable memory cells and method of making the same
    100.
    发明授权
    Memory cell array comprising individually addressable memory cells and method of making the same 有权
    包含单独可寻址存储单元的存储单元阵列及其制造方法

    公开(公告)号：US06888753B2

    公开(公告)日：2005-05-03

    申请号：US10680383

    申请日：2003-10-06

    申请人： Ronald Kakoschke ,  Josef Willer

    发明人： Ronald Kakoschke ,  Josef Willer

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  G11C11/34

    CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203

    摘要： A memory cell array comprises a plurality of memory transistors arranged in a two-dimensional array, each memory transistor having two source/drain regions arranged in a first direction of the memory cell array with a channel substrate region therebetween, and a gate structure arranged above the channel substrate region. The source/drain regions and channel substrate regions are formed in a substrate arranged on an insulating layer, with the channel substrate regions of memory transistors adjacent each other in the first direction being separated from each other by respective source/drain regions extending down to the insulating layer. The source/drain regions and the channel substrate regions of memory transistors adjacent each other in a second direction of the memory cell array furthermore are isolated from each other by trenches filled with insulating material and formed in the substrate so as to extend down to the insulating layer.

    摘要翻译： 存储单元阵列包括以二维阵列排列的多个存储晶体管，每个存储晶体管具有沿存储单元阵列的第一方向布置的两个源极/漏极区域，其间具有沟道衬底区域，并且栅极结构布置在 沟道衬底区域。 源极/漏极区域和沟道衬底区域形成在布置在绝缘层上的衬底中，其中在第一方向上彼此相邻的存储晶体管的沟道衬底区域通过相应的源极/漏极区域彼此分开， 绝缘层。 在存储单元阵列的第二方向上彼此相邻的存储晶体管的源极/漏极区域和沟道衬底区域进一步由填充有绝缘材料的沟槽彼此隔离，并形成在衬底中，以向下延伸到绝缘 层。