公开(公告)号：US08630114B2

公开(公告)日：2014-01-14

申请号：US13045975

申请日：2011-03-11

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: G11C11/40

CPC classification number: H01L27/1021 ,  G11C11/4097 ,  G11C13/0007 ,  G11C2211/4016 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/10802 ,  H01L27/11206 ,  H01L27/11578 ,  H01L29/7841

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks of memory cells. Word lines are arranged over the stacks of memory cells. Bit lines structures are coupled to multiple locations along the stacks of memory cells. Source line structures are coupled to multiple locations along each of the semiconductor material strips of the stacks. The bit line structures and the source line structures are between adjacent ones of the word lines.

Abstract translation: 3D存储器件包括多个脊形堆叠的存储器单元。 字线排列在存储器单元的堆叠之上。 位线结构沿着存储器单元的堆叠耦合到多个位置。 源极线结构沿堆叠的半导体材料条的每一个耦合到多个位置。 位线结构和源极线结构位于相邻的字线之间。

公开(公告)号：US08609554B2

公开(公告)日：2013-12-17

申请号：US13009502

申请日：2011-01-19

Applicant: Hang-Ting Lue ,  Yi-Hsuan Hsiao

Inventor： Hang-Ting Lue ,  Yi-Hsuan Hsiao

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L23/485 ,  H01L24/64 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/792

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. A first silicon-containing conductive material is formed on a substrate. A second silicon-containing conductive material is formed on the first silicon-containing conductive material. The first silicon-containing conductive material and the second silicon-containing conductive material have different dopant conditions. The first silicon-containing conductive material and the second silicon-containing conductive material are thermally oxidized for turning the first silicon-containing conductive material wholly into an insulating oxide structure, and the second silicon-containing conductive material into a silicon-containing conductive structure and an insulating oxide layer.

公开(公告)号：US08598032B2

公开(公告)日：2013-12-03

申请号：US13049303

申请日：2011-03-16

Applicant: Shih-Hung Chen ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L23/538 ,  H01L21/308

CPC classification number: H01L21/67069 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76838 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires a set of N etch masks to create up to and including 2N levels of interconnect contact regions at the stack of contact levels. According to some examples, 2x−1 contact levels are etched for each mask sequence number x, x being a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N. Methods create the interconnect contact regions aligned with landing areas at the contact levels.

Abstract translation: 三维堆叠IC器件在互连区域具有一层接触电平。 根据本发明的一些示例，其仅需要一组N个蚀刻掩模以在接触电平的叠层处产生多达且包括2N级的互连接触区域。 根据一些示例，对于每个掩码序列号x蚀刻2x-1接触电平，x是掩模的序列号，使得对于一个掩模x = 1，对于另一个掩模x = 2，依此类推，x = N 。 方法创建互连接触区域与接触层面上的着陆区域对齐。

公开(公告)号：US08574992B2

公开(公告)日：2013-11-05

申请号：US13240568

申请日：2011-09-22

Applicant: Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

IPC: H01L21/336 ,  G11C5/06

CPC classification number: H01L27/11206 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481

Abstract: A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding circuitry and the like, are formed as parts of the same patterned level of material. The same material layer can be used to form the contact pads and the conductive access lines by an etch process using a single mask. By forming the contact pads concurrently with the conductive lines, the patterned material of the contact pads can protect underlying circuit elements which could otherwise be damaged during patterning of the conductive lines.

Abstract translation: 描述了适用于低成本，高产量制造的用于三维（3D）存储器件的垂直互连架构。 用于3D存储器阵列的导电线（例如字线）和用于将阵列耦合到解码电路等的垂直连接器的接触焊盘形成为相同图案化材料层的部分。 可以使用相同的材​​料层通过使用单个掩模的蚀刻工艺形成接触焊盘和导电接入线。 通过与导电线同时形成接触焊盘，接触焊盘的图案化材料可以保护潜在的电路元件，否则在导电线图案化期间可能会损坏接触焊盘。

公开(公告)号：US20130264683A1

公开(公告)日：2013-10-10

申请号：US13443417

申请日：2012-04-10

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

IPC: H01L29/00 ,  H01L21/56

CPC classification number: H01L23/3192 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a base, a stacked structure and a doped layer. The stacked structure is formed on the base, wherein the stacked structure comprises a plurality of conductive strips and a plurality of insulating strips, one of the conductive strips is located between adjacent two insulating strips, the stacked structure has a first side wall, and a long edge of the first side wall is extended along a channel direction. The doped layer is formed in the first side wall, wherein the doped layer is formed by an ion implantation applied to the first side wall, and an acute angle is contained between an implantation direction of the ion implantation and the first side wall.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括基极，层叠结构和掺杂层。 堆叠结构形成在基底上，其中堆叠结构包括多个导电条和多个绝缘条，其中一个导电条位于相邻的两个绝缘条之间，该堆叠结构具有第一侧壁和 第一侧壁的长边缘沿着通道方向延伸。 掺杂层形成在第一侧壁中，其中通过施加到第一侧壁上的离子注入形成掺杂层，并且在离子注入的注入方向和第一侧壁之间包含锐角。

公开(公告)号：US08481388B2

公开(公告)日：2013-07-09

申请号：US12818057

申请日：2010-06-17

Applicant: Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

Inventor： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

IPC: H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/513

Abstract: A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.

Abstract translation: 非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。 存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。 具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。 在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

公开(公告)号：US08467219B2

公开(公告)日：2013-06-18

申请号：US13482843

申请日：2012-05-29

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: G11C5/06 ,  G11C16/04

CPC classification number: G11C5/06 ,  G11C5/02 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.

Abstract translation: 3D存储器件包括多个由绝缘材料隔开的导电材料条带形式的脊形叠层，排列成可通过解码电路耦合到读出放大器的位线。 导电材料条具有在脊形叠层的侧面上的侧表面。 布置成可以连接到行解码器的字线的多条导线垂直地延伸在多个脊形叠层上。 导线符合堆叠的表面。 存储器元件位于叠层和导电线上的导电条的侧表面之间的交叉点处的界面区域的多层阵列。 存储器元件是可编程的，如抗熔丝或电荷捕获结构。 3D存储器仅使用两层用于多层的关键掩模。

公开(公告)号：US20130075802A1

公开(公告)日：2013-03-28

申请号：US13240568

申请日：2011-09-22

Applicant: Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

IPC: H01L27/085 ,  H01L21/28

CPC classification number: H01L27/11206 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481

Abstract: A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding circuitry and the like, are formed as parts of the same patterned level of material. The same material layer can be used to form the contact pads and the conductive access lines by an etch process using a single mask. By forming the contact pads concurrently with the conductive lines, the patterned material of the contact pads can protect underlying circuit elements which could otherwise be damaged during patterning of the conductive lines.

Abstract translation: 描述了适用于低成本，高产量制造的用于三维（3D）存储器件的垂直互连架构。 用于3D存储器阵列的导电线（例如字线）和用于将阵列耦合到解码电路等的垂直连接器的接触焊盘形成为相同图案化材料层的部分。 可以使用相同的材​​料层通过使用单个掩模的蚀刻工艺形成接触焊盘和导电接入线。 通过与导电线同时形成接触焊盘，接触焊盘的图案化材料可以保护潜在的电路元件，否则在导电线图案化期间可能会损坏接触焊盘。

公开(公告)号：US08383512B2

公开(公告)日：2013-02-26

申请号：US13114931

申请日：2011-05-24

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Hong-Ji Lee ,  Chin-Cheng Yang

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Hong-Ji Lee ,  Chin-Cheng Yang

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L23/50 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/19 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method provides electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device. Each contact level comprises conductive and insulation layers. A portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level. A set of N masks is used to etch the contact openings up to and including 2N contact levels. Each mask is used to etch effectively half of the contact openings. When N is 3, a first mask etches one contact level, a second mask etches two contact levels, and a third mask etches four contact levels. A dielectric layer may be formed on the sidewalls of the contact openings. Electrical conductors may be formed through the contact openings with the dielectric layers electrically insulating the electrical conductors from the sidewalls.

Abstract translation: 一种方法提供了用于3-D堆叠IC器件的互连区域的接触电平堆叠的电连接。 每个接触层包括导电层和绝缘层。 去除任何上层的一部分以露出第一接触层并为每个接触层产生接触开口。 使用一组N个掩模来蚀刻直到并包括2N个接触电平的接触开口。 每个掩模用于有效地蚀刻半个接触开口。 当N为3时，第一掩模蚀刻一个接触电平，第二掩模蚀刻两个接触电平，并且第三掩模蚀刻四个接触电平。 电介质层可以形成在接触开口的侧壁上。 电导体可以通过接触开口形成，其中电介质层将电导体与侧壁电绝缘。

公开(公告)号：US20130003434A1

公开(公告)日：2013-01-03

申请号：US13612658

申请日：2012-09-12

Applicant: Hang-Ting Lue ,  Chih-Ping Chen

Inventor： Hang-Ting Lue ,  Chih-Ping Chen

IPC: G11C5/02

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823487 ,  H01L27/11578 ,  H01L29/792

Abstract: A method for operating a semiconductor structure is provided. The semiconductor structure comprises a substrate, a first stacked structure, a dielectric element, a conductive line, a first conductive island and a second conductive island. The first stacked structure is formed on the substrate. The first stacked structure comprises first conductive strips and first insulating strips stacked alternately. The first conductive strips are separated from each other by the first insulating strips. The dielectric element is formed on the first stacked structure. The conductive line is formed on the dielectric element. The first conductive island and the second conductive island on opposite sidewalls of the first stacked structure are separated from each other. The method for operating the semiconductor structure comprises respectively applying a first voltage to the first conductive island and applying a second voltage to the second conductive island.

Abstract translation: 提供了一种用于操作半导体结构的方法。 半导体结构包括基板，第一堆叠结构，电介质元件，导电线，第一导电岛和第二导电岛。 第一层叠结构形成在基板上。 第一堆叠结构包括交替堆叠的第一导电条和第一绝缘条。 第一导电条通过第一绝缘条彼此分开。 电介质元件形成在第一堆叠结构上。 导电线形成在电介质元件上。 第一层叠结构的相对侧壁上的第一导电岛和第二导电岛彼此分离。 用于操作半导体结构的方法包括分别向第一导电岛施加第一电压并向第二导电岛施加第二电压。