公开(公告)号：US08248103B2

公开(公告)日：2012-08-21

申请号：US13043873

申请日：2011-03-09

Applicant: Chang-Kyu Choi ,  Kyung-Hoon Kim

Inventor： Chang-Kyu Choi ,  Kyung-Hoon Kim

IPC: H03K19/0175

CPC classification number: H03K5/08 ,  H04L25/0264 ,  H04L25/028

Abstract: An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

Abstract translation: 半导体器件的输出电路包括：信号选择器，被配置为接收第一和第二输入数据信号，并响应于相位信号顺序地输出第一和第二输入数据信号; 以及输出电平控制器，被配置为基于第一和第二输入数据信号来控制信号选择器的输出信号的电压电平。

公开(公告)号：US08194496B2

公开(公告)日：2012-06-05

申请号：US13105431

申请日：2011-05-11

Applicant: Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

Inventor： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

IPC: G11C8/18

CPC classification number: H03H11/26

Abstract: Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

公开(公告)号：US08030981B2

公开(公告)日：2011-10-04

申请号：US12486320

申请日：2009-06-17

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: H03H11/26

CPC classification number: H03L7/0814 ,  G11C7/1045 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2272

Abstract: A semiconductor device includes a latency signal generating circuit for generating a latency signal corresponding CAS latency by measuring a delay amount reflected at a delay locked loop and reflecting the measured delay amount at a read command signal, and a delay locked loop for controlling an internal clock signal applied to the latency signal generating circuit corresponding to the read command and the latency signal. The semiconductor device includes an internal clock signal generating block configured to generate an internal clock signal, a latency generating block configured to generate a latency signal by synchronizing a read command signal with the internal clock signal at a time corresponding to a CAS latency value and a measured delay value, and an input controlling block configured to activate the reference clock signal using an external clock signal in response to the read command signal and the latency signal.

Abstract translation: 一种半导体器件包括等待时间信号发生电路，用于通过测量在延迟锁定环路处反映的延迟量并反映读取命令信号的测量延迟量来产生对应于CAS等待时间的等待时间信号，以及延迟锁定环路，用于控制内部时钟 信号被施加到对应于读命令和等待时间信号的等待时间信号发生电路。 半导体器件包括：内部时钟信号产生模块，用于产生内部时钟信号;等待时间产生模块，被配置为通过在与CAS等待时间值对应的时间同步读取命令信号和内部时钟信号来生成等待时间信号; 测量延迟值，以及输入控制块，被配置为响应于读取命令信号和等待时间信号，使用外部时钟信号激活参考时钟信号。

公开(公告)号：US20110227894A1

公开(公告)日：2011-09-22

申请号：US12946176

申请日：2010-11-15

Applicant: Yang-Hwa Choi ,  Seung-Kyu Lee ,  Kyung-Hoon Kim ,  Chul-Ho Kim ,  Se-Hyang Kim

Inventor： Yang-Hwa Choi ,  Seung-Kyu Lee ,  Kyung-Hoon Kim ,  Chul-Ho Kim ,  Se-Hyang Kim

IPC: G06F3/038

CPC classification number: G09G3/3655 ,  G09G2300/0814 ,  G09G2310/0281 ,  G09G2320/0252 ,  G09G2330/021

Abstract: A display device includes: a plurality of pixels; a data driver connected to the plurality of pixels by a plurality of data lines and applying data signals to the plurality of pixels; a scan driver connected to the plurality of pixels by a plurality of scan lines and applying scan signals to the plurality of pixels for the data signals to be applied to the plurality of pixels; a boost driver connected to the plurality of pixels by a plurality of boost lines and applying boost signals, boosting the pixel voltage charged to the plurality of pixels by the data signals, to the plurality of pixels; and a boost voltage maintaining unit applying a restoring voltage restoring the voltage in the plurality of boost lines by the scan signal to the plurality of boost lines. The voltage generated in the boost line by the coupling may be quickly restored and the crosstalk may be minimized, thereby improving the image quality.

Abstract translation: 显示装置包括：多个像素; 数据驱动器，其通过多条数据线连接到所述多个像素，并将数据信号施加到所述多个像素; 扫描驱动器，其通过多条扫描线连接到所述多个像素，并且将扫描信号施加到所述多个像素，以供应用于所述多个像素的数据信号; 升压驱动器，其通过多个升压线连接到所述多个像素，并且施加升压信号，通过所述数据信号将所述多个像素的像素电压升压到所述多个像素; 以及升压保持单元，通过所述扫描信号将多个升压线中的电压恢复到所述多个升压线路而施加恢复电压。 通过耦合在升压线中产生的电压可以被快速恢复，并且串扰可以被最小化，从而提高图像质量。

公开(公告)号：US07961008B2

公开(公告)日：2011-06-14

申请号：US11647491

申请日：2006-12-29

Applicant: Kyung-Hoon Kim ,  Tae-Heui Kwon

Inventor： Kyung-Hoon Kim ,  Tae-Heui Kwon

IPC: H03K19/094

CPC classification number: H03K19/0005

Abstract: A data output driving circuit includes a plurality of driving units that are set to have different impedance values from one another, and the number of driving units is less than the number of a plurality of required driving impedance values such that the driving units can obtain the plurality of required driving impedance values by a combination thereof, and a driving control unit that independently controls the operation of the plurality of driving units so as to obtain the plurality of driving impedance values required.

Abstract translation: 数据输出驱动电路包括被设定为彼此具有不同阻抗值的多个驱动单元，并且驱动单元的数量小于多个要求的驱动阻抗值的数量，使得驱动单元可以获得 通过其组合的多个所需的驱动阻抗值，以及独立地控制多个驱动单元的操作以获得所需的多个驱动阻抗值的驱动控制单元。

公开(公告)号：US07889594B2

公开(公告)日：2011-02-15

申请号：US12327312

申请日：2008-12-03

Applicant: Sang-Sic Yoon ,  Kyung-Hoon Kim

Inventor： Sang-Sic Yoon ,  Kyung-Hoon Kim

IPC: G11C11/00

CPC classification number: G11C8/18 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: A circuit which can reduce time taken by a clock alignment training operation in a semiconductor memory device is provided. The semiconductor memory device, which includes: a clock inputting unit configured to receive a system clock and a data clock; a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock, wherein the clock dividing unit determines a phase of the data division clock in response to an inversion division control signal; a phase dividing unit configured to generate a plurality of multiple phase data division clocks having respective predetermined phase differences in response to the data division clock; a data serializing unit configured to serialize predetermined parallel pattern data in correspondence with the multiple phase data division clocks; and a signal transmitting unit configured to transmit an output signal of the data serializing unit to the outside.

Abstract translation: 提供一种可以减少半导体存储器件中的时钟对准训练操作所花费的时间的电路。 所述半导体存储器件包括：时钟输入单元，被配置为接收系统时钟和数据时钟; 时钟分频单元，被配置为分频数据时钟的频率以产生数据分时钟，其中所述时钟分频单元响应于反相分配控制信号确定所述数据分时钟的相位; 相位分割单元，被配置为响应于所述数据分时钟产生具有相应的预定相位差的多个多相数据分时钟; 数据串行化单元，被配置为与多个相位数据分时钟对应地串行化预定的并行模式数据; 以及信号发送单元，被配置为将数据串行化单元的输出信号发送到外部。

公开(公告)号：US07881148B2

公开(公告)日：2011-02-01

申请号：US12277650

申请日：2008-11-25

Applicant: Kyung-Hoon Kim ,  Sang-Sic Yoon ,  Hong-Bae Kim

Inventor： Kyung-Hoon Kim ,  Sang-Sic Yoon ,  Hong-Bae Kim

IPC: G11C8/00 ,  G11C8/18 ,  H03K3/017

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C7/225

Abstract: A semiconductor memory device includes a clock supply portion for providing an external clock to the interior of the memory device, a clock transfer portion for transferring the clock from the clock supply portion to each of elements in the memory device and data output portions for outputting data in synchronism the clock from the clock transfer portion, wherein the clock from the clock supply portion to the clock transfer portion swings at a current mode logic (CML) level.

Abstract translation: 一种半导体存储器件，包括用于向存储器件内部提供外部时钟的时钟提供部分，用于将时钟从时钟供应部分传送到存储器件中的每个元件的时钟传送部分和用于输出数据的数据输出部分 同步来自时钟传送部分的时钟，其中从时钟提供部分到时钟传送部分的时钟以当前模式逻辑（CML）电平摆动。

公开(公告)号：US07876148B2

公开(公告)日：2011-01-25

申请号：US12344552

申请日：2008-12-28

Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

IPC: H03L7/093 ,  H03L7/095

CPC classification number: H03L7/095 ,  G01R29/0273 ,  H03K5/153 ,  H03K2005/00065 ,  H03K2005/00071 ,  Y10S331/02

Abstract: A low pass filter includes a driver unit configured to output a voltage proportional to an input pulse width, a charge/discharge unit configured to charge the output voltage of the driver unit, a comparator unit configured to compare an output voltage of the charge/discharge unit with a reference value to output a square wave signal, and a switching unit configured to switch the charge/discharge unit to an operation state, based on a bandwidth expansion signal.

Abstract translation: 低通滤波器包括被配置为输出与输入脉冲宽度成比例的电压的驱动器单元，被配置为对驱动器单元的输出电压进行充电的充电/放电单元，被配置为比较充电/放电的输出电压 具有参考值的单元以输出方波信号;以及切换单元，被配置为基于带宽扩展信号将充电/放电单元切换到操作状态。

公开(公告)号：US07855933B2

公开(公告)日：2010-12-21

申请号：US12165045

申请日：2008-06-30

Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

IPC: G11C8/00

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  H03K2005/00208 ,  H03L7/0805 ,  H03L7/083 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/24

Abstract: A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.

Abstract translation: 一种具有时钟同步电路的半导体存储器件，其能够执行期望的相位/频率锁定操作，而没有抖动峰化现象和使用注入锁定的振荡控制电压信号的模式抖动。 该装置包括锁相环，其检测反馈时钟信号和参考时钟信号之间的相位/频率差，以产生对应于检测到的相位/频率差的振荡控制电压信号，并产生对应于 振荡控制电压信号。 注入锁定振荡单元响应于振荡控制电压信号建立自由运行频率，并产生与参考时钟信号同步的内部时钟信号。

公开(公告)号：US07834664B2

公开(公告)日：2010-11-16

申请号：US12327112

申请日：2008-12-03

Applicant: Sang-Sic Yoon ,  Kyung-Hoon Kim

Inventor： Sang-Sic Yoon ,  Kyung-Hoon Kim

IPC: G01R25/00 ,  H03D13/00

CPC classification number: G06F1/08

Abstract: A semiconductor, which includes a first phase detecting unit configured to detect a phase of a second clock on the basis of a phase of a first clock, and generate a first detection signal corresponding to a result of the detection, a second phase detecting unit configured to detect a phase of a delayed clock, which is generated by delaying the second clock by a predetermined time, on the basis of the phase of the first clock, and generate a second detection signal corresponding to a result of the detection, and a logic level determining unit configured to determine a logic level of a feedback output signal according to the first detection signal, the second detection signal and the feedback output signal.

Abstract translation: 一种半导体，包括：第一相位检测单元，被配置为基于第一时钟的相位检测第二时钟的相位，并且生成与检测结果相对应的第一检测信号;第二相位检测单元，被配置为 基于第一时钟的相位来检测通过将第二时钟延迟预定时间而产生的延迟时钟的相位，并且生成与检测结果相对应的第二检测信号，以及逻辑 电平确定单元，被配置为根据第一检测信号，第二检测信号和反馈输出信号来确定反馈输出信号的逻辑电平。