公开(公告)号：US06953375B2

公开(公告)日：2005-10-11

申请号：US10813204

申请日：2004-03-29

申请人： Kie Y. Ahn ,  Leonard Forbes

发明人： Kie Y. Ahn ,  Leonard Forbes

IPC分类号： H01J9/02 ,  H01J9/00

CPC分类号： H01J1/3044 ,  H01J9/025

摘要： A field emission display includes a substrate and a plurality of emitters formed on columns on the substrate. The display also includes a porous dielectric layer formed on the substrate and the columns. The porous dielectric layer has an opening formed about each of the emitters and has a thickness substantially equal to a height of the emitters above the substrate. The porous dielectric layer may be formed by oxidation of porous polycrystalline silicon. The display also includes an extraction grid formed substantially in a plane defined by respective tips of the plurality of emitters and having an opening surrounding each tip of a respective one of the emitters. The display further includes a cathodoluminescent-coated faceplate having a planar surface formed parallel to and near the plane of tips of the plurality of emitters. The porous dielectric layer results in columns having less capacitance compared to prior art displays. Accordingly, less electrical power is required to charge and discharge the columns in order to drive the emitters. As a result, the display is able to form luminous images while consuming reduced electrical power compared to prior art displays.

摘要翻译： 场发射显示器包括衬底和形成在衬底上的列上的多个发射体。 显示器还包括形成在基板和列上的多孔介电层。 多孔电介质层具有围绕每个发射体形成的开口，其厚度基本上等于衬底上方的发射体的高度。 多孔介电层可以通过多孔多晶硅的氧化形成。 显示器还包括基本上形成在由多个发射器的各个尖端限定的平面中并且具有围绕相应一个发射器的每个尖端的开口的提取格栅。 显示器还包括阴极发光涂覆的面板，其具有平行于多个发射器的尖端平面并且靠近多个发射器的尖端的平面。 与现有技术的显示器相比，多孔介电层导致柱具有较小的电容。 因此，为了驱动发射器，需要较少的电功率对柱进行充电和放电。 结果，与现有技术的显示器相比，显示器能够形成发光图像同时消耗降低的电功率。

公开(公告)号：US06881627B2

公开(公告)日：2005-04-19

申请号：US10232268

申请日：2002-08-28

申请人： Leonard Forbes ,  Kie Y. Ahn

发明人： Leonard Forbes ,  Kie Y. Ahn

IPC分类号： H01L21/764 ,  G11C16/04 ,  G11C16/28 ,  H01L21/20 ,  H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L27/12 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66666 ,  G11C16/0416 ,  G11C16/28 ,  H01L21/28273 ,  H01L27/11556 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7889

摘要： Structures and method for Flash memory with ultra thin vertical body transistors are provided. The Flash memory includes an array of memory cells including floating gate transistors. Each floating gate transistor includes a pillar extending outwardly from a semiconductor substrate. The pillar includes a single crystalline first contact layer and a second contact layer vertically separated by an oxide layer. A single crystalline vertical transistor is formed along side of the pillar. The single crystalline vertical transistor includes an ultra thin single crystalline vertical body region which separates an ultra thin single crystalline vertical first source/drain region and an ultra thin single crystalline vertical second source/drain region. A floating gate opposes the ultra thin single crystalline vertical body region, and a control gate separated from the floating gate by an insulator layer.

摘要翻译： 提供了具有超薄垂直体晶体管的闪存的结构和方法。 闪速存储器包括包括浮动栅极晶体管的存储单元阵列。 每个浮栅晶体管包括从半导体衬底向外延伸的柱。 柱包括单晶第一接触层和由氧化物层垂直分隔的第二接触层。 沿着支柱的侧面形成单晶垂直晶体管。 单晶垂直晶体管包括分离超薄单晶垂直第一源极/漏极区域和超薄单晶垂直第二源极/漏极区域的超薄单晶垂直体区域。 浮动栅极与超薄单晶垂直体区域相对，并且通过绝缘体层与浮动栅极分离的控制栅极。

公开(公告)号：US06879017B2

公开(公告)日：2005-04-12

申请号：US10338178

申请日：2003-01-07

申请人： Kie Y. Ahn ,  Leonard Forbes ,  Paul A. Farrar

发明人： Kie Y. Ahn ,  Leonard Forbes ,  Paul A. Farrar

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L29/00

CPC分类号： H01L21/76877 ,  H01L21/7682 ,  H01L21/76886 ,  H01L23/53271 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10S438/933 ,  H01L2924/00

摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. The invention provides a new “trench-less” or “self-planarizing” method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance.

摘要翻译： 典型的集成电路制造需要用金属线互连数百万个微观晶体管和电阻器。 使金属丝与底层绝缘体齐平或共面需要在绝缘层中挖沟，然后用金属填充沟槽以形成导线。 本发明提供了一种制造共面金属线的新的“无沟槽”或“自平坦化”方法。 具体地，一个实施方案形成包括硅和锗的第一层; 氧化第一层的区域以限定氧化区域和非氧化区域; 并使铝或铝合金与非氧化区域反应。 该反应用铝代替或替代非氧化区域以形成与第一层共面的金属线。 另一步骤从氧化区域除去氧化锗以形成具有非常低介电常数的多孔绝缘体，由此降低电容。

公开(公告)号：US06858444B2

公开(公告)日：2005-02-22

申请号：US10600965

申请日：2003-06-20

申请人： Kie Y. Ahn ,  Leonard Forbes

发明人： Kie Y. Ahn ,  Leonard Forbes

IPC分类号： H01L21/28 ,  H01L27/115 ,  H01L29/51 ,  H01L29/78 ,  H01L21/00

CPC分类号： H01L21/28291 ,  H01L27/11502 ,  H01L29/516 ,  H01L29/78391

摘要： Integrated memory circuits, key components in thousands of electronic and computer products, have recently been made using ferroelectric memory transistors, which offer faster write cycles and lower power requirements than over conventional floating-gate transistors. One problem that hinders the continued down-scaling of conventional ferroelectric memory transistors is the vulnerability of their gate insulations to failure at thinner dimensions. Accordingly, the inventors devised unique ferroelectric gate structures, one of which includes a high-integrity silicon-oxide insulative layer, a doped titanium-oxide layer, a weak-ferroelectric layer, and a control gate. The doped titanium-oxide layer replaces a metal layer in the conventional ferroelectric gate structure, and the weak-ferroelectric layer replaces a conventional ferroelectric layer. These replacements reduce the permittivity mismatch found in conventional gate structures, and thus reduce stress on gate insulation layers, thereby improving reliability of ferroelectric memory transistors, particularly those with thinner gate insulation.

摘要翻译： 最近已经使用集成存储器电路，成千上万的电子和计算机产品中的关键部件，使用铁电存储晶体管，其提供比常规浮栅晶体管更快的写周期和更低的功率需求。 妨碍传统铁电存储晶体管继续缩小的一个问题是其栅极绝缘在较薄尺寸下的故障的脆弱性。 因此，本发明人设计了独特的铁电栅极结构，其中之一包括高完整性的氧化硅绝缘层，掺杂的氧化钛层，弱铁电层和控制栅极。 掺杂的氧化钛层代替传统的铁电栅极结构中的金属层，并且弱铁电层代替常规的铁电层。 这些替代物降低了传统栅极结构中所存在的介电常数不匹配，从而降低了栅极绝缘层的应力，从而提高了铁电存储晶体管的可靠性，特别是栅极绝缘更薄的晶体管。

公开(公告)号：US06853288B2

公开(公告)日：2005-02-08

申请号：US10719501

申请日：2003-11-21

申请人： Kie Y. Ahn ,  Leonard Forbes

发明人： Kie Y. Ahn ,  Leonard Forbes

IPC分类号： H01F5/00 ,  H01F17/00 ,  H01F17/04 ,  H01F41/04

CPC分类号： H01F41/046 ,  H01F5/003 ,  H01F17/0033 ,  H01F17/045 ,  H01L28/10 ,  Y10T29/4902

摘要： An inductor is fabricated on a substrate having a top surface and a bottom surface. The inductor includes a plurality of holes extending through the substrate, wherein the plurality of holes interconnect the top surface and the bottom surface of the substrate. The inductor also includes a plurality of conductive posts formed in the plurality of holes and a plurality of conductive segments formed on the top surface and on the bottom surface that interconnect the conductive posts such that a continuous conductive coil is formed. The inductor also includes a magnetic core that occupies substantially the entire volume enclosed by the conductive coil.

公开(公告)号：US06838763B2

公开(公告)日：2005-01-04

申请号：US10383654

申请日：2003-03-10

申请人： Kie Y. Ahn ,  Leonard Forbes

发明人： Kie Y. Ahn ,  Leonard Forbes

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/04

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2223/6622 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/00

摘要： A wireless communication system comprising a carrier having a top and a bottom surface, and a plurality of integrated circuit components for transmitting and receiving communication signals located on the top and bottom surfaces of the carrier. At least one passageway extends through the carrier, and conductive material extends through the passageway for electrically interconnecting the integrated circuit components located on the top and bottom surfaces of the carrier.

摘要翻译： 一种包括具有顶表面和底表面的载体的无线通信系统以及用于发送和接收位于载体的顶表面和底表面上的通信信号的多个集成电路部件。 至少一个通道延伸穿过载体，并且导电材料延伸穿过通道，用于将位于载体的顶表面和底表面上的集成电路部件电互连。

公开(公告)号：US06835111B2

公开(公告)日：2004-12-28

申请号：US09994511

申请日：2001-11-26

申请人： Kie Y. Ahn ,  Leonard Forbes

发明人： Kie Y. Ahn ,  Leonard Forbes

IPC分类号： H01J900

CPC分类号： H01J1/3044 ,  H01J9/025

摘要： A field emission display includes a substrate and a plurality of emitters formed on columns on the substrate. The display also includes a porous dielectric layer formed on the substrate and the columns. The porous dielectric layer has an opening formed about each of the emitters and has a thickness substantially equal to a height of the emitters above the substrate. The porous dielectric layer may be formed by oxidation of porous polycrystalline silicon. The display also includes an extraction grid formed substantially in a plane defined by respective tips of the plurality of emitters and having an opening surrounding each tip of a respective one of the emitters. The display further includes a cathodoluminescent-coated faceplate having a planar surface formed parallel to and near the plane of tips of the plurality of emitters. The porous dielectric layer results in columns having less capacitance compared to prior art displays. Accordingly, less electrical power is required to charge and discharge the columns in order to drive the emitters. As a result, the display is able to form luminous images while consuming reduced electrical power compared to prior art displays.

摘要翻译： 场发射显示器包括衬底和形成在衬底上的列上的多个发射体。 显示器还包括形成在基板和列上的多孔介电层。 多孔电介质层具有围绕每个发射体形成的开口，其厚度基本上等于衬底上方的发射体的高度。 多孔介电层可以通过多孔多晶硅的氧化形成。 显示器还包括基本上形成在由多个发射器的各个尖端限定的平面中并且具有围绕相应一个发射器的每个尖端的开口的提取格栅。 显示器还包括阴极发光涂覆的面板，其具有平行于多个发射器的尖端平面并且靠近多个发射器的尖端的平面。 与现有技术的显示器相比，多孔介电层导致柱具有较小的电容。 因此，为了驱动发射器，需要较少的电功率对柱进行充电和放电。 结果，与现有技术的显示器相比，显示器能够形成发光图像同时消耗降低的电功率。

公开(公告)号：US06817087B2

公开(公告)日：2004-11-16

申请号：US10100706

申请日：2002-03-18

申请人： Kie Y. Ahn ,  Leonard Forbes

发明人： Kie Y. Ahn ,  Leonard Forbes

IPC分类号： H01F706

CPC分类号： H01F17/0033 ,  H01F27/2804 ,  H01F37/00 ,  H01L27/08 ,  Y10S257/924 ,  Y10T29/4902 ,  Y10T29/49037 ,  Y10T29/49069 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49075

摘要： The invention relates to an inductor comprising a plurality of interconnected conductive segments interwoven with a substrate. The inductance of the inductor is increased through the use of coatings and films of ferromagnetic materials such as magnetic metals, alloys, and oxides. The inductor is compatible with integrated circuit manufacturing techniques and eliminates the need in many systems and circuits for large off chip inductors. A sense and measurement coil, which is fabricated on the same substrate as the inductor, provides the capability to measure the magnetic field or flux produced by the inductor. This on chip measurement capability supplies information that permits circuit engineers to design and fabricate on chip inductors to very tight tolerances.

公开(公告)号：US06815303B2

公开(公告)日：2004-11-09

申请号：US09069668

申请日：1998-04-29

申请人： Kie Y. Ahn ,  Leonard Forbes

发明人： Kie Y. Ahn ,  Leonard Forbes

IPC分类号： H01L21331

CPC分类号： H01L29/66287 ,  H01L29/41708

摘要： Many integrated circuits include a type of transistor known as a bipolar junction transistor, which has an emitter contact formed of polysilicon. Unfortunately, polysilicon has a relatively high electrical resistance that poses an obstacle to improving switching speed and current gain of bipolar transistors. Current fabrication techniques involve high temperature procedures that melt desirable low-resistance substitutes, such as aluminum, during fabrication. Accordingly, one embodiment of the invention provides an emitter contact structure that includes a polysilicon-carbide layer and a low-resistance aluminum, gold, or silver member to reduce emitter resistance. Moreover, to overcome manufacturing difficulties, the inventors employ a metal-substitution technique, which entails formation of a polysilicon emitter, and then substitution of metal for the polysilicon.

公开(公告)号：US06794246B2

公开(公告)日：2004-09-21

申请号：US10185155

申请日：2002-06-28

申请人： Leonard Forbes ,  Kie Y. Ahn

发明人： Leonard Forbes ,  Kie Y. Ahn

IPC分类号： H01L21336

CPC分类号： H01L27/112 ,  H01L27/11233 ,  H01L27/11803 ,  H01L29/42324 ,  H01L29/42368 ,  H01L29/66484 ,  H01L29/7831

摘要： One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and a second logic plane, each including a plurality of logic cells interconnected to implement a logical function. Forming the logic cells includes forming a horizontal substrate with a source region, a drain region, and a depletion mode channel region separating the source and the drain regions, and further includes forming a number of vertical gates located above different portions of the depletion mode channel region. At least one vertical gate is separated from the depletion mode channel region by a first oxide thickness, and at least one of the vertical gates is separated from the depletion mode channel region by a second oxide thickness. Other aspects and embodiments are provided herein.

摘要翻译： 本文公开的一个方面涉及一种用于形成可编程逻辑阵列的方法。 该方法的各种实施例包括形成第一逻辑平面和第二逻辑平面，每个逻辑平面和第二逻辑平面包括互连的多个逻辑单元以实现逻辑功能。 形成逻辑单元包括：形成具有分离源极区和漏极区的源极区，漏极区和耗尽模式沟道区的水平衬底，并且还包括形成位于耗尽模式沟道的不同部分上方的多个垂直栅极 地区。 至少一个垂直栅极与耗尽模式沟道区分离第一氧化物厚度，并且至少一个垂直栅极与耗尽模式沟道区分离第二氧化物厚度。 本文提供了其它方面和实施例。