Efficient transport flow processing on an accelerator
    91.
    发明申请
    Efficient transport flow processing on an accelerator 审中-公开
    加速器上高效的运输流程处理

    公开(公告)号:US20160330301A1

    公开(公告)日:2016-11-10

    申请号:US15146013

    申请日:2016-05-04

    Abstract: Data processing apparatus includes a host processor and a network interface controller (NIC), which is configured to couple the host processor to a packet data network. A memory holds a flow state table containing context information with respect to computational operations to be performed on multiple packet flows conveyed between the host processor and the network. Acceleration logic is coupled to perform the computational operations on payloads of packets in the multiple packet flows using the context information in the flow state table.

    Abstract translation: 数据处理装置包括主处理器和网络接口控制器(NIC),其被配置为将主机处理器耦合到分组数据网络。 存储器保存流状态表,该流状态表包含关于在主处理器和网络之间传送的多个分组流执行的计算操作的上下文信息。 加速逻辑被耦合以使用流状态表中的上下文信息对多个分组流中的分组的有效载荷执行计算操作。

    ADAPTIVE ROUTING CONTROLLED BY SOURCE NODE
    92.
    发明申请
    ADAPTIVE ROUTING CONTROLLED BY SOURCE NODE 有权
    由源节点控制的自适应路由

    公开(公告)号:US20160294715A1

    公开(公告)日:2016-10-06

    申请号:US14673892

    申请日:2015-03-31

    CPC classification number: H04L47/34 H04L45/22 H04L45/38 H04L47/122

    Abstract: A method in a network element that includes multiple interfaces for connecting to a communication network includes receiving from the communication network via an ingress interface a flow including a sequence of packets, and routing the packets to a destination of the flow via a first egress interface. A permission indication for re-routing the flow is received in the ingress interface. In response to receiving the permission indication, subsequent packets of the flow are re-routed via a second egress interface that is different from the first egress interface. Further re-routing of the flow is refrained from, until receiving another permission indication.

    Abstract translation: 包括用于连接到通信网络的多个接口的网络元件中的方法包括经由入口接口从通信网络接收包括一系列分组的流,以及经由第一出口接口将分组路由到流的目的地。 在入口接口中接收到重新路由流量的许可指示。 响应于接收到许可指示,流的后续分组经由与第一出口接口不同的第二出口接口重新路由。 直到收到另一个许可指示为止,进一步重新路由流。

    Network Adapter Providing Address Translation as a Service

    公开(公告)号:US20250028648A1

    公开(公告)日:2025-01-23

    申请号:US18353123

    申请日:2023-07-17

    Abstract: A network adapter including a host interface, a network interface, packet processing circuitry, and Translation-as-a-Service (TaaS) circuitry. The host interface is to communicate with a host over a peripheral bus. The network interface is to send and receive packets to and from a network for the host. The packet processing circuitry is to process the packets. The TaaS circuitry is integrated in the network adapter and is to (i) receive from a requesting device a request to translate an input address into a requested address in a requested address space, (ii) translate the input address into the one or more requested addresses, and (iii) return the one or more requested addresses to the requesting device.

    Methods and systems for inter-stack communication for logical volume management

    公开(公告)号:US12147716B2

    公开(公告)日:2024-11-19

    申请号:US17586417

    申请日:2022-01-27

    Abstract: Methods and systems provided herein involve extracting an input/output (I/O) operation from a packet received over an I/O pipeline, the I/O operation comprising either a read request to read data from at least one storage device or a write request to write data to the at least one storage device; determining that an address associated with the I/O operation exists in a lookup table that is provided for thin provisioning of the at least one storage device; performing one or more RAID calculations associated with the at least one storage device based on the address and the I/O operation; and accessing the at least one storage device to perform the I/O operation based on the one or more RAID calculations; and second processing component configured to carry out a second set of operations that occur when the address associated with the I/O operation does not exist in the lookup table.

    Data processing unit with transparent root complex

    公开(公告)号:US12117948B2

    公开(公告)日:2024-10-15

    申请号:US17976909

    申请日:2022-10-31

    CPC classification number: G06F13/28 G06F13/4221

    Abstract: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.

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