公开(公告)号：US20160330301A1

公开(公告)日：2016-11-10

申请号：US15146013

申请日：2016-05-04

Applicant: Mellanox Technologies Ltd.

Inventor： Shachar Raindel ,  Shlomo Raikin ,  Liran Liss

IPC: H04L29/06 ,  H04L12/851 ,  G06F21/60 ,  H04L12/801

Abstract: Data processing apparatus includes a host processor and a network interface controller (NIC), which is configured to couple the host processor to a packet data network. A memory holds a flow state table containing context information with respect to computational operations to be performed on multiple packet flows conveyed between the host processor and the network. Acceleration logic is coupled to perform the computational operations on payloads of packets in the multiple packet flows using the context information in the flow state table.

Abstract translation: 数据处理装置包括主处理器和网络接口控制器（NIC），其被配置为将主机处理器耦合到分组数据网络。 存储器保存流状态表，该流状态表包含关于在主处理器和网络之间传送的多个分组流执行的计算操作的上下文信息。 加速逻辑被耦合以使用流状态表中的上下文信息对多个分组流中的分组的有效载荷执行计算操作。

公开(公告)号：US20160294715A1

公开(公告)日：2016-10-06

申请号：US14673892

申请日：2015-03-31

Applicant: Mellanox Technologies Ltd.

Inventor： Shachar Raindel ,  Idan Burstein ,  Noam Bloch ,  Benny Koren ,  Barak Gafni ,  Dror Goldenberg ,  Liran Liss

IPC: H04L12/801 ,  H04L12/721 ,  H04L12/803 ,  H04L12/707

CPC classification number: H04L47/34 ,  H04L45/22 ,  H04L45/38 ,  H04L47/122

Abstract: A method in a network element that includes multiple interfaces for connecting to a communication network includes receiving from the communication network via an ingress interface a flow including a sequence of packets, and routing the packets to a destination of the flow via a first egress interface. A permission indication for re-routing the flow is received in the ingress interface. In response to receiving the permission indication, subsequent packets of the flow are re-routed via a second egress interface that is different from the first egress interface. Further re-routing of the flow is refrained from, until receiving another permission indication.

Abstract translation: 包括用于连接到通信网络的多个接口的网络元件中的方法包括经由入口接口从通信网络接收包括一系列分组的流，以及经由第一出口接口将分组路由到流的目的地。 在入口接口中接收到重新路由流量的许可指示。 响应于接收到许可指示，流的后续分组经由与第一出口接口不同的第二出口接口重新路由。 直到收到另一个许可指示为止，进一步重新路由流。

公开(公告)号：US08745276B2

公开(公告)日：2014-06-03

申请号：US13628187

申请日：2012-09-27

Applicant: Mellanox Technologies Ltd.

Inventor： Noam Bloch ,  Shachar Raindel ,  Haggai Eran ,  Liran Liss

IPC: G06F13/14 ,  G06F13/38

CPC classification number: H04L49/9089 ,  G06F12/08 ,  H04L69/321

Abstract: A method for data transfer includes receiving in an input/output (I/O) operation data to be written to a specified virtual address in a host memory. Upon receiving the data, it is detected that a first page that contains the specified virtual address is swapped out of the host memory. Responsively to detecting that the first page is swapped out, the received data are written to a second, free page in the host memory, and the specified virtual address is remapped to the free page.

公开(公告)号：US12284115B2

公开(公告)日：2025-04-22

申请号：US18312244

申请日：2023-05-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Adi Merav Horowitz ,  Omri Kahalon ,  Rabia Loulou ,  Gal Shalom ,  Aviad Yehezkel ,  Liel Yonatan Maman ,  Liran Liss

IPC: G06F15/173 ,  H04L47/122 ,  H04L47/19 ,  H04L47/2408 ,  H04L47/6295

Abstract: Multipathing for session-based remote direct memory access (SRDMA) may be used for congestion management. A given SRDMA session group may be associated with multiple SRDMA sessions, each having its own unique 5-tuple. A queue pair (QP) associated with the SRDMA session group may provide a packet for transmission using the SRDMA session group. The SRDMA session group may enable the packet to be transmitted using any of the associated SRDMA sessions. Congestion levels for each of the SRDMA sessions may be monitored and weighted. Therefore, when a packet is received, an SRDMA session may be selected based, at least, on the weight to enable routing of packets to reduce latency and improve overall system efficiency.

公开(公告)号：US12244670B2

公开(公告)日：2025-03-04

申请号：US18363005

申请日：2023-08-01

Applicant: Mellanox Technologies, Ltd.

Inventor： Liran Liss ,  Yamin Friedman ,  Michael Kagan ,  Diego Crupnicoff ,  Idan Burstein ,  Matty Kadosh ,  Tzah Oved ,  Dror Goldenberg ,  Ron Yuval Efraim ,  Alexander Eli Rosenbaum ,  Aviad Yehezkel ,  Rabia Loulou

IPC: H04L67/141 ,  G06F15/173 ,  H04L9/08 ,  H04L67/146 ,  H04L69/16

Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.

公开(公告)号：US12231495B2

公开(公告)日：2025-02-18

申请号：US18545057

申请日：2023-12-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Adi Merav Horowitz ,  Rabia Loulou ,  Omri Kahalon ,  Gal Shalom ,  Aviad Yehezkel ,  Asaf Schwartz ,  Liran Liss

IPC: G06F15/167 ,  H04L67/1097 ,  H04L67/146

Abstract: Systems and methods enable session sharing for session-based remote direct memory access (RDMA). Multiple queue pairs (QPs) can be added to a single session and/or session group where each of the QPs has a common remote. Systems and methods may query a session ID for an existing session group and then use the session ID with an add QP request to join additional QPs to an existing session. Newly added QPs may share one or more features with existing QPs of the session group, such as encryption parameters. Additionally, newly added QPs may be configured with different performance or quality of service requirements, thereby isolating performance, and permitting true scaling for high performance computing applications.

公开(公告)号：US20250028648A1

公开(公告)日：2025-01-23

申请号：US18353123

申请日：2023-07-17

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Eliav Bar-Ilan ,  Liran Liss

IPC: G06F12/1072 ,  H04L67/1097

Abstract: A network adapter including a host interface, a network interface, packet processing circuitry, and Translation-as-a-Service (TaaS) circuitry. The host interface is to communicate with a host over a peripheral bus. The network interface is to send and receive packets to and from a network for the host. The packet processing circuitry is to process the packets. The TaaS circuitry is integrated in the network adapter and is to (i) receive from a requesting device a request to translate an input address into a requested address in a requested address space, (ii) translate the input address into the one or more requested addresses, and (iii) return the one or more requested addresses to the requesting device.

公开(公告)号：US12147716B2

公开(公告)日：2024-11-19

申请号：US17586417

申请日：2022-01-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Omri Kahalon ,  Gal Shalom ,  Aviad Yehezkel ,  Liran Liss ,  Oren Duer ,  Rabie Loulou ,  Maxim Gurtovoy

IPC: G06F3/00 ,  G06F3/06

Abstract: Methods and systems provided herein involve extracting an input/output (I/O) operation from a packet received over an I/O pipeline, the I/O operation comprising either a read request to read data from at least one storage device or a write request to write data to the at least one storage device; determining that an address associated with the I/O operation exists in a lookup table that is provided for thin provisioning of the at least one storage device; performing one or more RAID calculations associated with the at least one storage device based on the address and the I/O operation; and accessing the at least one storage device to perform the I/O operation based on the one or more RAID calculations; and second processing component configured to carry out a second set of operations that occur when the address associated with the I/O operation does not exist in the lookup table.

公开(公告)号：US12119958B2

公开(公告)日：2024-10-15

申请号：US18349148

申请日：2023-07-09

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Idan Burstein ,  Liran Liss ,  Hillel Chapman ,  Dror Goldenberg ,  Michael Kagan ,  Aviad Yehezkel ,  Peter Paneah

IPC: H04L12/46 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

CPC classification number: H04L12/4625 ,  G06F13/4027 ,  G06F13/4208 ,  G06F15/17331 ,  H04L12/4633 ,  G06F2213/0026

Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.

公开(公告)号：US12117948B2

公开(公告)日：2024-10-15

申请号：US17976909

申请日：2022-10-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Liran Liss ,  Rabia Loulou ,  Idan Burstein ,  Tzuriel Katoa

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221

Abstract: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.