公开(公告)号：US20170345870A1

公开(公告)日：2017-11-30

申请号：US15291203

申请日：2016-10-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Dai-Ying Lee ,  Erh-Kun Lai

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: A resistive memory includes a semiconductor substrate, a dielectric layer, an insulating layer and a metal electrode layer. The semiconductor substrate has a top surface and a recess extending downwards into the semiconductor substrate from the top surface. The dielectric layer is disposed on the semiconductor substrate and has a first through-hole aligning the recess. The insulating layer is disposed in the first through-hole and the recess. The metal electrode layer is disposed on the insulating layer by which the metal electrode layer is isolated from the semiconductor substrate.

公开(公告)号：US09748262B1

公开(公告)日：2017-08-29

申请号：US15097335

申请日：2016-04-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Kuang-Hao Chiang

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/49

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/4916 ,  H01L29/495

Abstract: A memory structure and a manufacturing method thereof are provided. The memory structure includes a bottom oxide layer, a first conductive layer on the bottom oxide layer, a first insulation recess, a plurality of insulating layers on the first conductive layer, a plurality of second conductive layers, a second insulation recess, a channel layer on a sidewall of the second insulation recess, and a memory layer located between the channel layer and the second conductive layers. The first insulation recess has a first width and penetrates through the first conductive layer. The second conductive layers and the insulating layers are interlacedly stacked, and the second conductive layers are electrically isolated from the first conductive layer. The second insulation recess located on the first insulation recess has a second width larger than the first width and penetrates through the insulating layers and the second conductive layers.

公开(公告)号：US09627397B2

公开(公告)日：2017-04-18

申请号：US14803212

申请日：2015-07-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Dai-Ying Lee

IPC: H01L27/00 ,  H01L27/11556 ,  H01L21/768 ,  H01L21/28 ,  H01L27/11582 ,  H01L29/788 ,  H01L29/51 ,  H01L29/06 ,  H01L23/535 ,  H01L27/115

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/115 ,  H01L27/11582 ,  H01L29/0649 ,  H01L29/513 ,  H01L29/515 ,  H01L29/518 ,  H01L29/7883

Abstract: A memory device includes a semiconductor substrate, an isolation layer disposed on the semiconductor substrate, a first conductive layer disposed on the isolation layer, at least one contact plug passing through the isolation layer and electrically contacting the semiconductor substrate with the first conductive layer, a plurality of insulating layers disposed on the first conductive layer, a plurality of second conductive layers alternatively stacked with the insulating layers and insulated from the first conductive layer, a channel layer disposed on at least one sidewall of a first through opening and electrically contacting to the contact plug, wherein the first through opening passes through the insulating layers and the second conductive layers to expose the contact plug, and a memory layer disposed between the channel layer and the second conductive layers.

公开(公告)号：US09601506B2

公开(公告)日：2017-03-21

申请号：US14620281

申请日：2015-02-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai

IPC: H01L27/11 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, stacks, a blocking layer-trapping layer-tunneling layer structure, channel layers, a first insulating material and a dielectric layer. The stacks are formed on the substrate. Each stack comprises a group of alternating conductive strips and insulating strips as well as a first string select line formed on the group. The blocking layer-trapping layer-tunneling layer structure and the channel layers are formed conformally with the stacks. The first insulating material is formed between the stacks and covers portions of the channel layers. The dielectric layer is formed on portions of the channel layers that are not covered by the first insulating material. The semiconductor structure further comprises second string select lines formed between the stacks on the first insulating material, wherein the second string select lines are separated from the channel layers by the dielectric layer.

公开(公告)号：US09576972B2

公开(公告)日：2017-02-21

申请号：US14730340

申请日：2015-06-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Kuang-Hao Chiang

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423 ,  H01L21/764

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/31144 ,  H01L21/764 ,  H01L29/4234

Abstract: A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. Two stacked structures are formed a substrate. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers and a top insulating layer. A charge trapping structure and a channel layer are formed. The charge trapping structure includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched and part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the first dielectric layers and the second dielectric layers to connect the channel layer.

Abstract translation: 提供半导体器件及其半导体器件的制造方法。 该制造方法包括以下步骤。 两个堆叠结构形成基板。 每个堆叠结构包括多个栅极层，多个栅极绝缘层和顶部绝缘层。 形成电荷捕获结构和沟道层。 电荷捕获结构包括多个第一电介质层和多个第二电介质层。 蚀刻每个第一电介质层的一部分，蚀刻每个第二电介质层的一部分以暴露沟道层的一部分。 在第一电介质层和第二电介质层上形成着接垫层以连接沟道层。

公开(公告)号：US20170025428A1

公开(公告)日：2017-01-26

申请号：US14803212

申请日：2015-07-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Dai-Ying Lee

IPC: H01L27/115 ,  H01L21/28 ,  H01L23/535 ,  H01L29/51 ,  H01L29/06 ,  H01L21/768 ,  H01L29/788

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/115 ,  H01L27/11582 ,  H01L29/0649 ,  H01L29/513 ,  H01L29/515 ,  H01L29/518 ,  H01L29/7883

Abstract: A memory device includes a semiconductor substrate, an isolation layer disposed on the semiconductor substrate, a first conductive layer disposed on the isolation layer, at least one contact plug passing through the isolation layer and electrically contacting the semiconductor substrate with the first conductive layer, a plurality of insulating layers disposed on the first conductive layer, a plurality of second conductive layers alternatively stacked with the insulating layers and insulated from the first conductive layer, a channel layer disposed on at least one sidewall of a first through opening and electrically contacting to the contact plug, wherein the first through opening passes through the insulating layers and the second conductive layers to expose the contact plug, and a memory layer disposed between the channel layer and the second conductive layers.

Abstract translation: 存储器件包括半导体衬底，设置在半导体衬底上的隔离层，设置在隔离层上的第一导电层，至少一个通过隔离层并使半导体衬底与第一导电层电接触的接触插塞， 布置在第一导电层上的多个绝缘层，多个第二导电层，交替地层叠有绝缘层并与第一导电层绝缘;沟道层，设置在第一通孔的至少一个侧壁上，并与 接触插塞，其中所述第一通孔穿过所述绝缘层和所述第二导电层以暴露所述接触插塞，以及设置在所述沟道层和所述第二导电层之间的存储层。

公开(公告)号：US09514982B2

公开(公告)日：2016-12-06

申请号：US14518050

申请日：2014-10-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai

IPC: H01L27/115 ,  H01L21/768

CPC classification number: H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate having a trench, a stacked strip structure formed in the trench, and at least a conductive structure. The stacked strip structure includes a plurality of interlaced conductive strips and insulating strips. Each of the conductive strips has a horizontal conductive segment and two vertical conductive segments connected to the corresponding horizontal conductive segment. Each of the insulating strips has a horizontal insulating segment and two vertical insulating segments. The conductive structure is electrically connected to at least one of the conductive strips. The stacked strip structure has a horizontal stacked portion corresponding to the horizontal conductive segments and two vertical stacked portions corresponding to the vertical conductive segments, wherein a width of the vertical stacked portions is larger than a thickness of the horizontal stacked portion.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括具有沟槽的衬底，形成在沟槽中的堆叠带状结构，以及至少导电结构。 堆叠的带状结构包括多个隔行导电条和绝缘条。 每个导电条具有水平导电段和连接到对应的水平导电段的两个垂直导电段。 每个绝缘条具有水平绝缘段和两个垂直绝缘段。 导电结构电连接到至少一个导电条。 堆叠的带状结构具有对应于水平导电段的水平堆叠部分和对应于垂直导电段的两个垂直堆叠部分，其中垂直堆叠部分的宽度大于水平堆叠部分的厚度。

公开(公告)号：US09484356B2

公开(公告)日：2016-11-01

申请号：US14474399

申请日：2014-09-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a stack of alternate conductive layers and insulating layers, an opening, an oxide layer and a conductor. The stack is formed on the substrate. The opening penetrates through the stack. The oxide layer is formed on a sidewall of the opening. The conductor is filled into the opening. The conductor is separated from the sidewall of the opening by only the oxide layer.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括衬底，交替导电层和绝缘层的堆叠，开口，氧化物层和导体。 堆叠形成在基板上。 开口穿过堆叠。 氧化物层形成在开口的侧壁上。 导体填充到开口中。 导体仅通过氧化物层与开口的侧壁分离。

公开(公告)号：US20160284722A1

公开(公告)日：2016-09-29

申请号：US14665103

申请日：2015-03-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/306 ,  H01L21/469 ,  H01L21/311 ,  H01L21/28 ,  H01L21/768 ,  H01L29/04 ,  H01L29/24 ,  H01L29/16 ,  H01L29/423 ,  H01L21/441 ,  H01L21/465 ,  H01L21/31 ,  H01L21/4757 ,  H01L23/528 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/465 ,  H01L21/469 ,  H01L21/47573 ,  H01L27/11565 ,  H01L29/66833 ,  H01L29/66969 ,  H01L29/7926

Abstract: A memory device including a substrate, at least one first stacked structure and at least one second stacked structure disposed on the substrate is provided. The first stacked structure includes a plurality of alternately stacked metal layers and oxide layers. The second stacked structure is disposed adjacent to the first stacked structure and includes a plurality of alternately stacked semiconductor layers and oxide layers. The metal layers of the first stacked structure are connected to the semiconductor layers of the second stacked structure.

Abstract translation: 提供一种存储器件，其包括衬底，至少一个第一堆叠结构和设置在衬底上的至少一个第二堆叠结构。 第一堆叠结构包括多个交替层叠的金属层和氧化物层。 第二堆叠结构设置成与第一层叠结构相邻，并且包括多个交替堆叠的半导体层和氧化物层。 第一堆叠结构的金属层连接到第二层叠结构的半导体层。

公开(公告)号：US09455403B1

公开(公告)日：2016-09-27

申请号：US14838500

申请日：2015-08-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Feng-Min Lee ,  Yu-Yu Lin ,  Dai-Ying Lee

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/1233 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises an access device, a dielectric layer, a barrier layer, a first interlayer conductor, a first barrier liner, a second interlayer conductor, a second barrier liner, a memory element and a top electrode layer. The access device has two terminals. The dielectric layer covers the access device. The barrier layer is disposed on the dielectric layer. The first and second interlayer conductors are connected to the two terminals, respectively. The first and second barrier liners are disposed on sidewalls of the first and second interlayer conductors, respectively. The memory element is disposed on the first interlayer conductor. The top electrode layer is disposed on the barrier layer and the memory element and covers the memory element.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括存取装置，电介质层，阻挡层，第一层间导体，第一阻挡衬垫，第二层间导体，第二阻挡衬垫，存储元件和顶电极层。 接入设备有两个终端。 电介质层覆盖接入装置。 阻挡层设置在电介质层上。 第一和第二层间导体分别连接到两个端子。 第一和第二阻挡衬垫分别设置在第一和第二层间导体的侧壁上。 存储元件设置在第一层间导体上。 顶部电极层设置在阻挡层和存储元件上并覆盖存储元件。