公开(公告)号：US10162556B2

公开(公告)日：2018-12-25

申请号：US15685926

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Federico Tiziani

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/38 ,  G06F9/50 ,  G11C14/00 ,  G11C13/00

Abstract: Various embodiments comprise devices and methods to manage multiple memory types and reconfigure partitions in a memory device as directed by a host. In one embodiment, the device is to manage logical memory partitioning on each of multiple memory devices that are based on differing, hybrid-memory technologies, the device is further to hide an actual storage media type of the multiple memory devices from the host through abstracted logical interface blocks. Additional devices and methods are described.

公开(公告)号：US10146477B2

公开(公告)日：2018-12-04

申请号：US15246735

申请日：2016-08-25

Applicant: Micron Technology, Inc.

Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

IPC: G06F3/06

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

公开(公告)号：US09880772B2

公开(公告)日：2018-01-30

申请号：US14860326

申请日：2015-09-21

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Graziano Mirichigni ,  Gianfranco Santopietro ,  Gianfranco Ferrante ,  Emanuele Confalonieri

IPC: G06F3/06

CPC classification number: G06F3/0643 ,  G06F3/061 ,  G06F3/0679

Abstract: A memory device includes a memory component and controller circuitry. The memory component stores data and the controller circuitry receives, from a host electronic device, one or more commands of a memory system protocol. The one or more commands include at least one write command, the write command comprising one or more blocks of data to be stored in the memory component. Further, the one or more commands include metadata, attributes, or both related to the one or more blocks of data. The controller circuitry interprets and executes the one or more commands. Accordingly, the blocks are stored in the memory component. Further, the controller circuitry of the memory device has access to the metadata, attributes or both.

公开(公告)号：US09824004B2

公开(公告)日：2017-11-21

申请号：US14506414

申请日：2014-10-03

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio

IPC: G06F12/02 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F12/023 ,  G06F3/0659 ,  G06F12/0246 ,  G06F13/1642

Abstract: Methods and apparatuses are disclosed for requesting ready status information from a memory. One example apparatus includes a memory and a host coupled to the memory. The host is configured to provide a plurality of memory access requests to the memory, to request ready status information regarding whether the memory is ready to execute a memory access request of the plurality of memory access requests, and to request execution of the memory access request responsive to the ready status information.

公开(公告)号：US09454310B2

公开(公告)日：2016-09-27

申请号：US14181089

申请日：2014-02-14

Applicant: Micron Technology, Inc.

Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0679 ,  G06F3/0688

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Abstract translation: 本公开包括用于命令排队的装置和方法。 许多实施例包括从主机在存储器系统处接收排队的命令请求，从存储器系统向主机发送指示存储器系统准备好在存储器系统的命令队列中接收命令的命令响应，以及 响应于发送命令响应，从所述主机接收在所述存储器系统处的所述命令的命令描述符块。

公开(公告)号：US20150100744A1

公开(公告)日：2015-04-09

申请号：US14506414

申请日：2014-10-03

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F3/0659 ,  G06F12/0246 ,  G06F13/1642

Abstract: Methods and apparatuses are disclosed for requesting ready status information from a memory. One example apparatus includes a memory and a host coupled to the memory. The host is configured to provide a plurality of memory access requests to the memory, to request ready status information regarding whether the memory is ready to execute a memory access request of the plurality of memory access requests, and to request execution of the memory access request responsive to the ready status information.

Abstract translation: 公开了用于从存储器请求就绪状态信息的方法和装置。 一个示例性设备包括存储器和耦合到存储器的主机。 主机被配置为向存储器提供多个存储器访问请求，以请求关于存储器是否准备好执行多个存储器访问请求的存储器访问请求的就绪状态信息，并且请求执行存储器访问请求 响应就绪状态信息。

公开(公告)号：US20140223087A1

公开(公告)日：2014-08-07

申请号：US14247783

申请日：2014-04-08

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Federico Tiziani

IPC: G06F9/50 ,  G11C14/00 ,  G06F12/02

CPC classification number: G06F3/0644 ,  G06F3/0607 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0637 ,  G06F3/0685 ,  G06F9/5077 ,  G06F12/0223 ,  G06F12/0238 ,  G06F12/0246 ,  G06F13/385 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2213/3804 ,  G06F2213/3854 ,  G11C13/0002 ,  G11C13/0004 ,  G11C14/009 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

Abstract translation: 各种实施例包括装置和方法，包括如由主机指导的在存储器装置中重新配置分区的方法。 该方法包括通过第一接口控制器管理命令以映射不具有属性增强集合的第一存储器的部分，以及通过第二接口控制器映射具有属性增强集合的第二存储器的部分。 描述附加的装置和方法。

公开(公告)号：US12293803B2

公开(公告)日：2025-05-06

申请号：US17943706

申请日：2022-09-13

Applicant: Micron Technology, Inc.

Inventor： William Yu ,  Daniele Balluchi ,  Chad B. Erickson ,  Danilo Caraccio

IPC: G11C16/04 ,  G11C29/10 ,  G11C29/12 ,  G11C29/38

Abstract: Methods, systems, and devices related to built-in self-test burst patterns based on architecture of memory. A controller can be coupled to a memory device. The controller can include built-in self-test (BIST) circuitry. The BIST circuitry can include registers configured to store respective write burst patterns and read burst patterns based on an architecture of the memory device.

公开(公告)号：US12235722B2

公开(公告)日：2025-02-25

申请号：US18216160

申请日：2023-06-29

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Sforzin

IPC: G06F11/10

Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.

公开(公告)号：US20250013458A1

公开(公告)日：2025-01-09

申请号：US18894289

申请日：2024-09-24

Applicant: Micron Technology, Inc.

Inventor： Niccolo Izzo ,  Alessandro Orlando ,  Danilo Caraccio ,  David Hulton

IPC: G06F8/65 ,  H04L9/08

Abstract: Methods, systems, and devices for techniques for managing offline identity upgrades are described. A memory system may receive a command to update a device identifier for a device identifier composition engine (DICE) associated with the memory system. The memory system may generate an updated device identifier, at a first software layer of a set of software layers of the DICE, based on receiving the command. The memory system may decrypt a device specific key (DSK) stored at a read-only memory device of the memory system based on the received command, and sign the updated device identifier using the DSK based on decrypting the DSK. The memory system may execute one or more operations associated with the first software layer of the set of software layers of the DICE based on the signed updated device identifier.