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    Methods of forming microelectronic devices
    92.
    发明授权
    Methods of forming microelectronic devices 有权

    公开(公告)号：US12041769B2

    公开(公告)日：2024-07-16

    申请号：US18047245

    申请日：2022-10-17

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli

    IPC: H10B43/50 ,  G11C5/02 ,  G11C5/06 ,  H01L23/538 ,  H10B41/27 ,  H10B43/27

    CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L23/5386 ,  H10B43/27 ,  H10B43/50

    Abstract: A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    93.
    发明公开
    Integrated Assemblies and Methods of Forming Integrated Assemblies 审中-公开

    公开(公告)号：US20240164093A1

    公开(公告)日：2024-05-16

    申请号：US18415928

    申请日：2024-01-18

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  Alyssa N. Scarbrough ,  John D. Hopkins

    IPC: H10B41/27 ,  G11C5/06 ,  H10B43/27

    CPC classification number: H10B41/27 ,  G11C5/06 ,  H10B43/27

    Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped-semiconductor-material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.

    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
    98.
    发明授权
    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US11856764B2

    公开(公告)日：2023-12-26

    申请号：US17223359

    申请日：2021-04-06

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  John D. Hopkins

    IPC: H01L21/00 ,  H10B41/27 ,  H01L21/768 ,  H10B43/27

    CPC classification number: H10B41/27 ,  H01L21/76802 ,  H01L21/76889 ,  H10B43/27

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor tier between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material and comprise metal material. After the horizontally-elongated lines are formed, conductive material is formed in a lower of the first tiers and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

    SELF-ALIGNED ETCHING TECHNIQUES FOR MEMORY FORMATION
    99.
    发明公开
    SELF-ALIGNED ETCHING TECHNIQUES FOR MEMORY FORMATION 审中-公开

    公开(公告)号：US20230395704A1

    公开(公告)日：2023-12-07

    申请号：US17804997

    申请日：2022-06-01

    Applicant: Micron Technology, Inc.

    Inventor： John Hopkins ,  Jordan D. Greenlee

    IPC: H01L29/66 ,  H01L27/1157 ,  H01L29/792

    CPC classification number: H01L29/66833 ,  H01L29/792 ,  H01L27/1157

    Abstract: Methods, systems, and devices for self-aligned etching techniques for memory formation are described. A memory device may include a stack of alternating materials and a pillar extending through the stack of alternating materials, where the stack of alternating materials and the pillar may form a set of multiple memory cells. A polysilicon material may be formed above the pillar, where the polysilicon material may be associated with a selector device for the memory cells. A masking material may be formed above the polysilicon material and the stack of alternating materials, where the masking material may be aligned with the polysilicon material and may have a width that is greater than a width of the polysilicon material and the pillar. The masking material may prevent the polysilicon material, the pillar, and a portion of the stack of alternating materials beneath the masking material from being removed during an etching operation.

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