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公开(公告)号：US11960360B1
公开(公告)日：2024-04-16
申请号：US17934452
申请日：2022-09-22
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
CPC classification number: G06F11/1068 , G06F11/0772 , G06F11/0793
Abstract: Methods, systems, and devices for redundancy-based error detection in a memory device are described. A memory device may read multiple copies of a codeword from memory and generate for each codeword copy an error detection bit that indicates whether the memory device detected an error in that codeword. Additionally, the memory device may compare the codeword copies and generate one or more match bits that indicate whether corresponding portions of the codewords match. Using a combination of the error detection bits and the match bits, the memory device may determine the error status of each codeword.
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公开(公告)号：US20240111626A1
公开(公告)日：2024-04-04
申请号：US17959902
申请日：2022-10-04
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer
CPC classification number: G06F11/1068 , G06F11/0772 , G06F11/0784
Abstract: Methods, systems, and devices for error status determination at a memory device are described. A memory device may generate, based on syndrome bits for a codeword read from a memory, an error detection signal for the codeword that indicates whether an error has been detected in the codeword. The memory device may generate, based on the syndrome bits, an error correction signal for the codeword that indicates whether an error has been corrected in the codeword. And the memory device may provide an indication of the error detection signal and an indication of the error correction signal to a host device.
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公开(公告)号：US11947806B2
公开(公告)日：2024-04-02
申请号：US17505028
申请日：2021-10-19
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm , Scott D. Van De Graaff , Todd J. Plum , Mark D. Ingram
CPC classification number: G06F3/0616 , G06F3/0655 , G06F3/0679
Abstract: Methods, systems, and devices for life expectancy monitoring for memory devices are described. A memory device may monitor a parameter of a component of the memory device or the memory device overall, and may determine whether the parameter satisfies a threshold. The parameter may represent or be associated with a lifetime of the component, a level of wear of the component, or an operating parameter violation of the component, or any combination thereof. The memory device may communicate, to a host device, an indication of the parameter satisfying the threshold, and the host device may use the information in the indication to adjust one or more parameters associated with operating the memory device, among other example operations.
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公开(公告)号：US11929134B2
公开(公告)日：2024-03-12
申请号：US17807625
申请日：2022-06-17
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer
CPC classification number: G11C29/46 , G11C7/1009 , G11C29/12005 , G11C29/4401
Abstract: Implementations described herein relate to performing a memory built-in self-test and indicating a status of the memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is enabled. The memory device may set a DMI bit of the memory device to a first value and perform the memory built-in self-test based on identifying that the memory built-in self-test is enabled. The memory device may set the DMI bit of the memory device to a second value based on a completion of the memory built-in self-test.
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公开(公告)号：US11899982B2
公开(公告)日：2024-02-13
申请号：US18100654
申请日：2023-01-24
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0673 , G06F21/79 , G06F12/1441 , G06F12/1466
Abstract: Methods, systems, and devices for command block management are described. A memory device may receive a command (e.g., from a host device). The memory device may determine whether the command is defined by determining if the command is included within a set of defined commands. In the case that a received command is absent from the set of defined commands (e.g., the command is undefined), the memory device may block the command from being decoded for execution by the memory device. In some cases, the memory device may switch from a first operation mode to a second operation mode based on receiving an undefined command. The second operation mode may restrict an operation of the memory device, while the first mode may be less restrictive, in some cases. Additionally or alternatively, the memory device may indicate the undefined command to another device (e.g., the host device).
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Patent Agency Ranking
公开(公告)号：US20230418708A1
公开(公告)日：2023-12-28
申请号：US18213732
申请日：2023-06-23
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
CPC classification number: G06F11/1068 , G06F11/1044 , G06F11/326 , G06F11/3037 , G06F11/0772
Abstract: Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.
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公开(公告)号：US11842080B2
公开(公告)日：2023-12-12
申请号：US17724216
申请日：2022-04-19
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Mark D. Ingram , Scott E. Schaefer , Scott D. Van De Graaff , Todd Jackson Plum
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F11/3058 , G06F11/3065
Abstract: Methods, systems, and devices for memory device health evaluation at a host device are described. The health evaluation relates to a host device that is associated with a memory device that monitors and reports health information, such as one or more parameters associated with a status of the memory device. The memory device may transmit the health information to the host device, which may perform one or more operations and may transmit the health information to a device of another entity of a system (e.g., ecosystem) including the host device. The host device may include one or more circuits for transmitting and processing the health information, such as a system health engine, a safety engine, a communication component, or a combination thereof. Based on a determination by the host device or information received from an external device, the host device may transmit a command to the memory device.
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公开(公告)号：US20230395182A1
公开(公告)日：2023-12-07
申请号：US17862082
申请日：2022-07-11
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer
CPC classification number: G11C29/52 , G11C29/023 , G11C7/22
Abstract: Methods, systems, and devices for differential strobe fault indication are described. A memory device may be configured to indicate a fault using a read strobe signal. The read strobe signal may be a read data strobe (RDQS) signal, such as a true RDQS (RDQS_t) signal or a complement RDQS (RDQS_c) signal. In some examples, the memory device may indicate the fault based on a characteristic of the read strobe signal, such as a pattern of the read strobe signal, a voltage level of the read strobe signal, a difference between a first read strobe signal and a second read strobe signal, or any combination thereof. In some examples, a host device may indicate to the memory device which characteristic of the read strobe signal the memory device is to use to indicate the fault.
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公开(公告)号：US11775385B2
公开(公告)日：2023-10-03
申请号：US17580284
申请日：2022-01-20
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer
IPC: G06F11/10 , H03M13/29 , G11C11/408 , G11C11/4091 , G11C11/22
CPC classification number: G06F11/1068 , H03M13/2906 , G11C11/221 , G11C11/4087 , G11C11/4091
Abstract: Methods, systems, and devices for targeted command/address parity low lift are described. A memory device receives a command (e.g., a write command or a read command) from a host device over a first set of pins and performs data transfer over a second set of pins with the host device according to the command. The memory device exchanges a first parity bit associated with the command with the host device, and generates a second parity bit based on the command. A parity result bit is subsequently generated based, at least in part, on the first parity bit and the second parity bit.
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公开(公告)号：US20230231574A1
公开(公告)日：2023-07-20
申请号：US18098995
申请日：2023-01-19
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer
CPC classification number: H03M13/1111 , H03M13/43 , H03M13/611
Abstract: Methods, systems, and devices for syndrome check functionality to differentiate between error types are described. A host system, a memory system, or some combination of both may include syndrome check circuitry to provide enhanced error diagnostic capabilities for data communicated between the host system and the memory system. The syndrome check circuitry may receive a first signal from the memory system indicating whether the memory system detected and attempted to correct an error in the data and may receive a second signal from the host system indicating whether the host system detected an error in the received data. The syndrome check circuitry may compare the first signal and the second signal using a set of logic gates to differentiate between different combinations of errors detected at one or both of the memory system or the host system.
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