公开(公告)号：US20050118755A1

公开(公告)日：2005-06-02

申请号：US10999270

申请日：2004-11-29

申请人： Li-Te Lin ,  Fang-Chen Cheng ,  Huin-Jer Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Li-Te Lin ,  Fang-Chen Cheng ,  Huin-Jer Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L29/40

CPC分类号： H01L21/31116 ,  H01L21/32137 ,  H01L21/32139

摘要： A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.

摘要翻译： 在半导体衬底上限定用于MOSFET器件的图案化导电栅极结构的方法包括在半导体衬底上形成导电层并在导电层上形成覆盖绝缘体层。 在覆盖绝缘体层上形成抗反射涂层（ARC）层，并且在ARC层上形成图案化的光刻胶形状。 使用光致抗蚀剂形状作为蚀刻掩模的第一蚀刻步骤限定了由ARC形状和封盖绝缘体形状组成的堆叠。 使用堆叠作为蚀刻掩模的第二蚀刻步骤限定了导电层中的图案化的导电栅极结构。

公开(公告)号：US20050106888A1

公开(公告)日：2005-05-19

申请号：US10714207

申请日：2003-11-14

申请人： Yuan-Hung Chiu ,  Ming-Ching Chang ,  Hun-Jan Tao

发明人： Yuan-Hung Chiu ,  Ming-Ching Chang ,  Hun-Jan Tao

IPC分类号： G03F7/42 ,  H01L21/302 ,  H01L21/306 ,  H01L21/311 ,  H01L21/461 ,  H01L21/768

CPC分类号： H01L21/31116 ,  G03F7/427 ,  H01L21/02046 ,  H01L21/02063 ,  H01L21/31138 ,  H01L21/76802 ,  H01L21/76814

摘要： An integrated process flow including a plasma step for removing oxide residues following oxygen ashing of a photoresist layer is disclosed. The oxide removal step is effective in preventing micro mask defects and is preferably performed in the same process chamber used for the oxygen ashing step and for a subsequent plasma etch used for pattern transfer. The oxide removal step takes less than 60 seconds and involves a halogen containing plasma that is generated from one or more of NF3, Cl2, CF4, CH2F2, and SF6. Optionally, HBr or a fluorocarbon CXFYHZ where x and y are integers and z is an integer or is equal to 0 may be used alone or with one of the aforementioned halogen containing gases. The oxide removal step may be incorporated in a variety of applications including a damascene scheme, shallow trench (STI) fabrication, or formation of a gate electrode in a transistor.

摘要翻译： 公开了一种集成工艺流程，其包括用于除去光致抗蚀剂层的氧灰化之后的氧化物残余物的等离子体步骤。 氧化物去除步骤在防止微掩模缺陷方面是有效的，并且优选在用于氧灰化步骤的相同处理室和用于图案转移的后续等离子体蚀刻中进行。 氧化物去除步骤需要少于60秒，并且涉及从NF 3，Cl 2，CF 4，...中的一个或多个产生的含卤素等离子体， SUB 2，CH 2，2 F 2和SF 6。 可选地，HBr或碳氟化合物其中x和y是整数，z是整数或等于0可以是 可以单独使用或与上述含卤素气体中的一种一起使用。 氧化物去除步骤可以结合在各种应用中，包括镶嵌方案，浅沟槽（STI）制造或在晶体管中形成栅电极。

公开(公告)号：US06867084B1

公开(公告)日：2005-03-15

申请号：US10263541

申请日：2002-10-03

申请人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Fang-Cheng Chen ,  Hun-Jan Tao

发明人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Fang-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/80

CPC分类号： H01L21/2652 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.

摘要翻译： 描述了场效应晶体管栅极结构和制造具有高k栅极介电材料和高k隔离物的栅极结构的方法。 首先在具有源极/漏极区域的硅衬底上沉积的虚拟有机或无机膜中蚀刻栅极图案或沟槽。 然后将高k电介质材料衬垫沉积在所有暴露的表面上。 然后将过多的多晶硅栅极导体膜沉积在沟槽内和沟槽上，以提供足够的覆盖层。 然后通过化学机械抛光或蚀刻方法对多晶硅进行平面化，使得在该步骤期间去除虚拟膜表面顶部的高k材料膜。 在最后的步骤中，将虚设薄膜放开，留下最终的晶体管栅极结构，其中高k栅极电介质和围绕栅极导体多晶硅的高k隔离层，整个栅极结构被制成以形成FET器件 硅衬底。

公开(公告)号：US06821880B1

公开(公告)日：2004-11-23

申请号：US10725138

申请日：2003-12-01

申请人： Hun-Jan Tao ,  Chao-Cheng Chen

发明人： Hun-Jan Tao ,  Chao-Cheng Chen

IPC分类号： H01L214763

CPC分类号： H01L21/76814 ,  H01L21/67155 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76838

摘要： A process of dual damascene or damascene. The dual damascene process entails providing an etching apparatus, a DCM machine and a wafer, the wafer having a metal line, a stop layer, a dielectric layer, a contact, and a photoresist layer. The dielectric layer and the contact are etched in the etching apparatus to form a trench. The photoresist and the contact are ashed in the DCM machine. Finally the wafer is wet cleaned.

摘要翻译： 一个双镶嵌或镶嵌的过程。 双镶嵌工艺需要提供蚀刻装置，DCM机器和晶片，晶片具有金属线，阻挡层，介电层，接触和光致抗蚀剂层。 在蚀刻装置中蚀刻介电层和接触以形成沟槽。 在DCM机器中将光致抗蚀剂和接触物灰化。 最后将晶片湿式清洗。

公开(公告)号：US06764903B1

公开(公告)日：2004-07-20

申请号：US10427451

申请日：2003-04-30

申请人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21336

CPC分类号： H01L21/28123 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for forming a patterned target layer from a blanket target layer employs a pair of blanket hard mask layers laminated upon the blanket target layer. A patterned third mask layer is formed thereover. The method also employs four separate etch steps. One etch step is an anisotropic etch step for forming a patterned upper lying hard mask layer from the blanket upper lying hard mask layer. The patterned upper lying hard mask layer is then isotropically etched in a second etch step to form an isotropically etched patterned upper lying hard mask layer. The method is particularly useful for forming gate electrodes of diminished linewidths and enhanced dimensional control within semiconductor products.

摘要翻译： 从覆盖目标层形成图案化目标层的方法采用层叠在覆盖目标层上的一对覆盖层硬掩模层。 在其上形成图案化的第三掩模层。 该方法还采用四个独立的蚀刻步骤。 一个蚀刻步骤是用于从橡皮布上面的硬掩模层形成图案化的上卧硬掩模层的各向异性蚀刻步骤。 然后在第二蚀刻步骤中各向同性蚀刻图案化的上卧硬掩模层，以形成各向同性蚀刻的图案化的上面的硬掩模层。 该方法对于形成半导体产品中线宽减小和尺寸控制增强的栅电极特别有用。

公开(公告)号：US06498067B1

公开(公告)日：2002-12-24

申请号：US10139021

申请日：2002-05-02

申请人： Baw-Ching Perng ,  Ming-Huang Tsai ,  Ju-Wang Hsu ,  Hun-Jan Tao

发明人： Baw-Ching Perng ,  Ming-Huang Tsai ,  Ju-Wang Hsu ,  Hun-Jan Tao

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L29/6656

摘要： A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, has been developed. The process features formation of additional insulator spacer shapes on top portions of sides of a gate structure in which an initial insulator spacer had been removed during an over etch cycle used for definition of the initial insulator spacer. The re-establishment of insulator spacer shapes provides a composite insulator spacer offering reduced risk of gate to substrate leakage or shorts, that can occur during a subsequent salicide procedure from the presence of metal silicide stringers or ribbons formed on, and residing on the composite insulator spacer.

摘要翻译： 已经开发了在MOSFET栅极结构的侧面上形成复合绝缘体间隔物的工艺。 该工艺特征是在栅极结构的侧面的顶部部分上形成额外的绝缘体间隔物形状，其中在用于限定初始绝缘体间隔物的过蚀刻循环期间已经去除了初始绝缘体间隔物。 重新建立绝缘体间隔物形状提供了一种复合绝缘体间隔物，其降低了栅极与衬底泄漏或短路的风险，这可能在随后的自对准硅化物过程中发生，从存在金属硅化物桁条或形成在复合绝缘体上的带状物 间隔

公开(公告)号：US06472335B1

公开(公告)日：2002-10-29

申请号：US09175019

申请日：1998-10-19

申请人： Chia-Shiung Tsai ,  Yao-Yi Cheng ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Yao-Yi Cheng ,  Hun-Jan Tao

IPC分类号： H01L2131

CPC分类号： H01L21/0214 ,  H01L21/02118 ,  H01L21/022 ,  H01L21/02343 ,  H01L21/31111 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3124 ,  H01L21/3144 ,  H01L21/31629 ,  H01L21/3185 ,  H01L21/76801 ,  Y10S438/906 ,  Y10S438/958 ,  Y10S438/964

摘要： The present invention provides a method improving the adhesion between inter metal dielectric (IMD) layers by performing a HF dip etch to treat the surface of an oxide, silicon nitride or Silicon oxynitride insulating layer before an overlying low-K layer is formed. The present invention provides a method of fabricating a low-K IMD layer 20 over an oxide, Silicon oxynitride (SiON), or nitride IMD layer 14 with improved adhesion. First, a 1st inter metal dielectric (IMD) layer 14 is formed over a substrate. Next, the invention's novel HF dip etch is performed on the 1st IMD layer 14 to form a treated surface 16. Next, a 2nd BMD layer composed of a low-K material is formed over the rough surface 16 of the 1st IMD layer 14. The treated surface 16 improves the adhesion between a 1st IMD layer oxide (oxide, SiN or SiON) and a low k layer. Subsequent photoresist strip steps do not cause the 1st IMI layer 14 and the 2nd IMD layer 20 (low-K dielectric) to peel.

摘要翻译： 本发明提供一种通过在形成上覆低K层之前进行HF浸渍蚀刻来处理氧化物，氮化硅或氮氧化硅绝缘层的表面来改善金属间电介质（IMD）层之间的粘合力的方法。 本发明提供了一种在氧化物，氮氧化硅（SiON）或氮化物IMD层14上制备低K IMD层20的方法，其具有改善的粘合性。 首先，在衬底上形成第一金属间介电层（IMD）层14。 接下来，在第一IMD层14上进行本发明的新型HF浸渍蚀刻以形成处理表面16.接下来，在第一IMD层14的粗糙表面16上形成由低K材料构成的第二BMD层。 经处理的表面16改善了第一IMD层氧化物（氧化物，SiN或SiON）和低k层之间的粘合性。 随后的光刻胶条步骤不会导致第一IMI层14和第二IMD层20（低K电介质）剥离。

公开(公告)号：US06410424B1

公开(公告)日：2002-06-25

申请号：US09837599

申请日：2001-04-19

申请人： Ming-Huan Tsai ,  Chung-Long Chang ,  Chii-Ming Wu ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Chung-Long Chang ,  Chii-Ming Wu ,  Hun-Jan Tao

IPC分类号： H01L214763

CPC分类号： H01L21/76804 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76829 ,  H01L21/76831 ,  Y10S438/975

摘要： A new processing sequence is provided for the creation of openings in layers of dielectric. Over a semiconductor surface are successively deposited an etch stop layer, a layer of dielectric and a hard mask layer. An opening is etched in the hard mask layer, the main opening is etched through the layer of dielectric and the etch stop layer. The surface is wet cleaned, after which a thin layer of silicon oxide is CVD deposited over the inside surfaces of the created opening. This thin layer of CVD oxide is subjected to argon sputter, providing of the critical dimensions of the upper region of the opening. Then the process continues with the deposition of the barrier metal, the filling of the opening with a conducting material to create the metal plug and the polishing of the surface of the deposited conducting material.

摘要翻译： 提供了一种新的处理顺序，用于在电介质层中产生开口。 在半导体表面上依次沉积蚀刻停止层，电介质层和硬掩模层。 在硬掩模层中蚀刻开口，通过电介质层和蚀刻停止层蚀刻主开口。 表面被湿清洗，之后在所产生的开口的内表面上CVD沉积薄层的氧化硅。 对CVD氧化物薄层进行氩溅射，提供开口上部区域的临界尺寸。 然后，该过程继续阻挡金属的沉积，用导电材料填充开口以产生金属塞和抛光沉积的导电材料的表面。

公开(公告)号：US6165881A

公开(公告)日：2000-12-26

申请号：US177185

申请日：1998-10-23

申请人： Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/665 ,  H01L21/0276 ,  H01L21/31116

摘要： I A method is achieved for removing a hardmask from a feature on a semiconductor wafer. The method comprises the following phases: depositing a buffer layer overall; etching back the buffer layer in an etching apparatus to expose the hardmask; etching the hardmask in the etching apparatus; and etching of the remaining buffer layer in the etching apparatus.

摘要翻译： I实现了从半导体晶片上的特征去除硬掩模的方法。 该方法包括以下阶段：整体沉积缓冲层; 在蚀刻装置中蚀刻缓冲层以暴露硬掩模; 在蚀刻装置中蚀刻硬掩模; 并蚀刻在蚀刻装置中的剩余缓冲层。

公开(公告)号：US6130167A

公开(公告)日：2000-10-10

申请号：US270593

申请日：1999-03-18

申请人： Hun-Jan Tao ,  Shu-Chin Yang ,  Chao-Cheng Chen

发明人： Hun-Jan Tao ,  Shu-Chin Yang ,  Chao-Cheng Chen

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/308

CPC分类号： H01L21/02071 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76814 ,  H01L21/76888 ,  H01L21/31116

摘要： A process used to prevent attack of an aluminum based structure, exposed in a non-fully landed via hole, from solvents used during the wet stripping cycle, performed to remove the via hole defining photoresist shape, has been developed. The process features the formation of a protective aluminum oxide layer, on the exposed side of the aluminum based structure, via use of a plasma treatment, performed in an H.sub.2 O/N.sub.2 ambient. The H.sub.2 O/N.sub.2 plasma treatment procedure is performed after a dry plasma, photoresist stripping step, but prior to a final wet photoresist stripping step. The aluminum oxide layer offers protection of the exposed regions of the aluminum structure, located in the non-fully landed via hole, from reaction or corrosion, that can result from exposure of aluminum to the solvents used in the final wet photoresist stripping cycle.

摘要翻译： 已经开发了一种用于防止暴露在非完全着陆的通孔中的铝基结构从在湿式剥离循环期间使用的溶剂的侵蚀的过程，以去除限定光致抗蚀剂形状的通孔。 该方法的特征在于在基于铝的结构的暴露侧上通过使用在H 2 O / N 2环境中进行的等离子体处理形成保护性氧化铝层。 H 2 O / N 2等离子体处理程序在干等离子体，光致抗蚀剂剥离步骤之后，但在最后的湿光致抗蚀剂剥离步骤之前进行。 氧化铝层提供保护位于非完全着陆的通孔中的铝结构的暴露区域不受反应或腐蚀的影响，这可能是由于将铝暴露于最终湿光致抗蚀剂剥离循环中使用的溶剂而导致的。