公开(公告)号：US06509226B1

公开(公告)日：2003-01-21

申请号：US09670741

申请日：2000-09-27

申请人： Venkatachalam C. Jaiprakash ,  Jack Mandelman ,  Ramachandra Divakaruni ,  Rajeev Malik ,  Mihel Seitz

发明人： Venkatachalam C. Jaiprakash ,  Jack Mandelman ,  Ramachandra Divakaruni ,  Rajeev Malik ,  Mihel Seitz

IPC分类号： H01L218242

CPC分类号： H01L27/10861

摘要： Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide. A thin polysilicon layer is deposited over the planarized surface and an active area (M) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The M mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches. An AA oxidation is performed, the isolation trenches are filled with high density plasma (HDP) oxide and planarized to the top surface of the AA pad nitride. Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying top oxide. The etch support (ES) nitride liner is deposited, and the ES mask is patterned to open the support areas. The ES nitride, thin polysilicon layer and top oxide are etched from the exposed areas. A sacrificial oxidation is applied along with well implants, support gate oxidation and support gate polysilicon deposition. Using the etch array (EA) mask, the support gate polysilicon is opened in the array. The ES nitride is removed selective to the underlying silicon layer, protecting the top oxide. The gate stack is deposited and patterned and the process continues to completion.

摘要翻译： 包含垂直MOSFET阵列的DRAM器件的处理通过将垂直MOSFET的阵列栅极导体（GC）多晶硅平坦化到顶部氧化物的顶表面进行。 在平坦化表面上沉积薄多晶硅层，并沉积有源区（M）衬垫氮化物和原硅酸四乙酯（TEOS）堆叠。 M掩模用于将焊盘层打开到硅表面，并且使用浅沟槽隔离（STI）蚀刻来形成隔离沟槽。 执行AA氧化，隔离沟槽填充有高密度等离子体（HDP）氧化物，并且平坦化到AA衬垫氮化物的顶表面。 在隔离沟槽（IT）平坦化之后，剥离AA衬垫氮化物，薄硅层用作保护底层氧化物的蚀刻停止层。 沉积蚀刻载体（ES）氮化物衬垫，并且将ES掩模图案化以打开支撑区域。 从暴露的区域蚀刻ES氮化物，薄多晶硅层和顶部氧化物。 牺牲氧化与井注入一起施加，支持栅极氧化和支撑栅极多晶硅沉积。 使用蚀刻阵列（EA）掩模，在阵列中打开支撑栅极多晶硅。 对于下层硅层选择性地除去ES氮化物，保护顶部氧化物。 沉积栅极堆叠并图案化，并且该工艺继续完成。

公开(公告)号：US06503798B1

公开(公告)日：2003-01-07

申请号：US09609168

申请日：2000-06-30

申请人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Herbert L. Ho ,  Akira Sudo

发明人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Herbert L. Ho ,  Akira Sudo

IPC分类号： H01L21336

CPC分类号： H01L27/10867

摘要： A method and structure for a dynamic random access device which includes a substrate having a trench, a conductor in the trench, a transistor adjacent the trench and a conductive strap electrically connecting the conductor and the transistor, wherein the strap comprises a plurality of strap conductors and the strap has a lower resistance than the conductor. The conductor comprises a first material having a first resistance and the strap comprises a second material different than the first material having a second resistance, wherein the second resistance is lower than the first resistance. The plurality of strap conductors comprises at least two electrically connected strap conductors, and a first strap conductor is adjacent the conductor and a second strap conductor is adjacent the transistor and the first strap conductor has an improved interface with the conductor. The strap comprises a lip strap, wherein the strap forms an L-shape. At least one of the plurality of the strap conductors is contiguous with a corner of the trench, and the plurality of strap conductors comprises a first strap conductor and a second strap conductor and the conductor is contiguous with the first strap conductor and the second strap conductor such that the second strap conductor and the conductor form an L-shape.

摘要翻译： 一种用于动态随机存取装置的方法和结构，其包括具有沟槽的衬底，沟槽中的导体，与沟槽相邻的晶体管和电连接导体和晶体管的导电带，其中带包括多个带状导体 并且带子具有比导体更低的电阻。 导体包括具有第一电阻的第一材料，并且带包括不同于具有第二电阻的第一材料的第二材料，其中第二电阻低于第一电阻。 多个带状导体包括至少两个电连接的带状导体，并且第一带导体与导体相邻，并且第二带导体与晶体管相邻，并且第一带导体具有与导体的改进的界面。 带子包括唇带，其中带子形成L形。 所述多个带状导体中的至少一个与所述沟槽的角部邻接，并且所述多个带状导体包括第一带状导体和第二带状导体，并且所述导体与所述第一带状导体和所述第二带状导体 使得第二带状导体和导体形成L形。

公开(公告)号：US06495876B1

公开(公告)日：2002-12-17

申请号：US09609288

申请日：2000-06-30

申请人： Gary Bronner ,  Ramachandra Divakaruni ,  Yoichi Takegawa

发明人： Gary Bronner ,  Ramachandra Divakaruni ,  Yoichi Takegawa

IPC分类号： H01L27108

CPC分类号： H01L21/3003 ,  H01L27/10867

摘要： A method and structure for a DRAM device which includes a trench within an insulator, a conductor within the trench, a transistor adjacent a first side of the trench, and a shallow trench isolation region formed within a top portion of the conductor on a second side of the trench, opposite the first side, wherein the top portion of the conductor has a curved shape at an edge of the shallow trench isolation region. The curved shape comprises a conductive strap and electrically connects the conductor and the single crystal where the transistor is formed, further comprising a collar oxide surrounding the top portion of the conductor, the collar oxide controlling a shape and location of the curved shape. The curved shape is formed by hydrogen annealing, and may be convex, or concave. The DRAM further comprising a collar oxide extending into the shallow trench isolation region on the second side.

摘要翻译： 一种用于DRAM器件的方法和结构，其包括绝缘体内的沟槽，沟槽内的导体，与沟槽的第一侧相邻的晶体管，以及形成在第二侧的导体的顶部内的浅沟槽隔离区 所述沟槽的第一侧相对，其中所述导体的顶部在所述浅沟槽隔离区域的边缘处具有弯曲形状。 弯曲形状包括导电带并且电连接导体和形成晶体管的单晶，还包括围绕导体顶部的环形氧化物，该环形氧化物控制弯曲形状的形状和位置。 弯曲形状由氢退火形成，并且可以是凸形或凹形。 DRAM还包括延伸到第二侧上的浅沟槽隔离区域的环状氧化物。

公开(公告)号：US06448131B1

公开(公告)日：2002-09-10

申请号：US09929182

申请日：2001-08-14

申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy M. Cohen ,  Ramachandra Divakaruni ,  Christian Lavoie ,  Fenton R. McFeely

发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy M. Cohen ,  Ramachandra Divakaruni ,  Christian Lavoie ,  Fenton R. McFeely

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L29/66181 ,  Y10S438/964

摘要： A method for increasing the trench capacitor surface area is provided. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal. Once the metal is deposited in the trench, the method is self-limited. Shrinking the trench to its original width can be obtained by subsequent silicon deposition or by diffusion of silicon from a cap layer through the silicide.

摘要翻译： 提供了一种用于增加沟槽电容器表面积的方法。 利用金属硅化物粗糙化沟槽壁的方法由于硅化物被去除之后的沟槽表面积的增加而增加了电容。 可以通过改变一个或多个以下参数来控制沟槽壁的粗糙化：金属的密度，金属膜厚度，硅化物相以及金属的选择。 一旦金属沉积在沟槽中，该方法是自限制的。 通过随后的硅沉积或通过硅化物从盖层扩散硅可以获得将沟槽缩小至原始宽度。

公开(公告)号：US06429068B1

公开(公告)日：2002-08-06

申请号：US09897868

申请日：2001-07-02

申请人： Ramachandra Divakaruni ,  Ulrike Gruening ,  Jack A. Mandelman ,  Larry Nesbit ,  Carl Radens

发明人： Ramachandra Divakaruni ,  Ulrike Gruening ,  Jack A. Mandelman ,  Larry Nesbit ,  Carl Radens

IPC分类号： H01L218242

CPC分类号： H01L27/10891 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10894

摘要： A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.

摘要翻译： 用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域中制造具有硅化多晶硅层的垂直MOSFET DRAM单元，着陆焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠。 该工艺消除了对M0金属化层的需要。

公开(公告)号：US06426247B1

公开(公告)日：2002-07-30

申请号：US09764824

申请日：2001-01-17

申请人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rajesh Rengarajan

发明人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rajesh Rengarajan

IPC分类号： H01L21338

CPC分类号： H01L27/10888 ,  H01L23/485 ,  H01L27/10861 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a memory device having low bitline capacitance, comprising: providing a gate conductor stack structure on a silicon substrate, said gate stack structure having a gate oxide layer, a polysilicon layer, a silicide layer, and a top dielectric nitride layer; oxidizing sidewalls of said gate oxide stack; forming sidewall spacers on the sidewalls of said gate conductor stack, said sidewall spacers comprising a thin layer of nitride having a thickness ranging from about 50 to about 250 angstroms; overlaying the gate structure with a thin nitride liner having a thickness ranging from about 25 to about 150 angstroms; depositing an insulative oxide layer over the gate structure; polishing the insulative oxide layer down to the level of the nitride liner of the gate structure; patterning and etching the insulative oxide layer to expose said nitride liner; forming second sidewall spacers over said first sidewall spacers, said second sidewall spacers comprising an oxide layer having a thickness ranging from about 100 to about 400 angstroms; and, depositing and planarizing a layer of polysilicon covering said gate structure and the sidewall spacers.

摘要翻译： 一种用于形成具有低位线电容的存储器件的方法，包括：在硅衬底上提供栅极导体堆叠结构，所述栅堆叠结构具有栅极氧化层，多晶硅层，硅化物层和顶部电介质氮化物层; 氧化所述栅极氧化层的侧壁; 在所述栅极导体堆叠的侧壁上形成侧壁间隔物，所述侧壁间隔物包括厚度范围为约50至约250埃的薄氮化物层; 用具有约25至约150埃的厚度的薄氮化物衬垫覆盖栅极结构; 在栅极结构上沉积绝缘氧化物层; 将绝缘氧化物层抛光到栅极结构的氮化物衬垫的水平面; 图案化和蚀刻绝缘氧化物层以暴露所述氮化物衬垫; 在所述第一侧壁间隔物上形成第二侧壁间隔物，所述第二侧壁间隔物包括厚度范围为约100至约400埃的氧化物层; 并且沉积和平坦化覆盖所述栅极结构和侧壁间隔物的多晶硅层。

公开(公告)号：US06406962B1

公开(公告)日：2002-06-18

申请号：US09761931

申请日：2001-01-17

申请人： Paul D. Agnello ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Paul D. Agnello ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21336

CPC分类号： H01L29/78648 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/78642

摘要： The present invention relates to an apparatus and method of forming one or more FETs having a vertical trench-formed double-gate, with a plurality of nitride layers having oxide marker etch-stop layers provided periodically there-through, thereby adapting the FETs to have a plurality of selectable gate lengths. The present invention provides for control and formation of gate lengths scaled down to about 5 nm to about 100 nm, preferably from about 5 nm to about 50 nm. The plurality of pad nitride layers with the oxide etch-stop layers provide for the present FET to be connected to a plurality of contacts having a variety of connection depths corresponding to the gate lengths used, by etching a plurality of via in the pad nitride layers whereby such vias stop at selected ones of the etch-stop layers to provide vias adapted to connect with the selected ones of such contacts. Additional gate material may be deposited over a top surface of the selected plurality of nitride layers to allow for contacts to the gate electrodes of any given FET.

摘要翻译： 本发明涉及一种形成具有垂直沟槽形成的双栅极的一个或多个FET的装置和方法，其中多个氮化物层具有周期性地设置在其上的氧化物标记蚀刻停止层，从而使FET具有 多个可选择的栅极长度。 本发明提供控制和形成尺寸缩小到约5nm至约100nm，优选约5nm至约50nm的栅极长度。 具有氧化物蚀刻停止层的多个衬垫氮化物层通过蚀刻衬垫氮化物层中的多个通孔来提供本FET连接到具有对应于所使用的栅极长度的各种连接深度的多个触点 由此这些通孔在选定的蚀刻停止层处停止以提供适于与所选择的这些触点连接的通孔。 附加的栅极材料可以沉积在所选择的多个氮化物层的顶表面上，以允许与任何给定FET的栅电极的接触。

公开(公告)号：US08759172B2

公开(公告)日：2014-06-24

申请号：US13449433

申请日：2012-04-18

申请人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

发明人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

IPC分类号： H01L21/336

CPC分类号： H01L29/517 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/66545

摘要： A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.

摘要翻译： 一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。 栅极电介质盖形成在金属栅极导体上。 栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。 接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

公开(公告)号：US20130277764A1

公开(公告)日：2013-10-24

申请号：US13449433

申请日：2012-04-18

申请人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

发明人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/517 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/66545

摘要： A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.

摘要翻译： 一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。 栅极电介质盖形成在金属栅极导体上。 栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。 接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

公开(公告)号：US20130256802A1

公开(公告)日：2013-10-03

申请号：US13430755

申请日：2012-03-27

申请人： Hemanth Jagannathan ,  Ramachandra Divakaruni ,  Unoh Kwon ,  Vijay Narayanan ,  Ravikumar Ramachandran

发明人： Hemanth Jagannathan ,  Ramachandra Divakaruni ,  Unoh Kwon ,  Vijay Narayanan ,  Ravikumar Ramachandran

IPC分类号： H01L27/088 ,  H01L21/283

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel.

摘要翻译： 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括与其它层组合提供约4.4eV或更低的功函数的材料，并且可以包括选自碳化钽，金属氮化物和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。 任选地，可以在通道中引入碳掺杂。