公开(公告)号：US08609303B2

公开(公告)日：2013-12-17

申请号：US13237651

申请日：2011-09-20

申请人： Chikaaki Kodama ,  Toshiya Kotani ,  Hiromitusu Mashita ,  Fumiharu Nakajima

发明人： Chikaaki Kodama ,  Toshiya Kotani ,  Hiromitusu Mashita ,  Fumiharu Nakajima

IPC分类号： G03F1/38 ,  G03F1/68

CPC分类号： G03F1/36 ,  G03F1/38

摘要： According to a mask pattern generating method of the embodiments, an undesired pattern, which is transferred onto a substrate due to an auxiliary pattern when an on-substrate pattern is formed on the substrate by using a mask pattern in which the auxiliary pattern is placed, is extracted as an undesired transfer pattern. Then, the mask pattern is corrected by changing a size of the auxiliary pattern according to a size and a position of the undesired transfer pattern.

摘要翻译： 根据实施例的掩模图案生成方法，当通过使用其中放置辅助图案的掩模图案在衬底上形成衬底上图案时，由于辅助图案而转移到衬底上的不需要的图案， 被提取为不期望的转移模式。 然后，通过根据不希望的转印图案的尺寸和位置改变辅助图案的尺寸来校正掩模图案。

公开(公告)号：US08438527B2

公开(公告)日：2013-05-07

申请号：US13426965

申请日：2012-03-22

申请人： Satomi Nakamura ,  Toshiya Kotani ,  Kazuhito Kobayashi ,  Akiko Mimotogi ,  Chikaaki Kodama

发明人： Satomi Nakamura ,  Toshiya Kotani ,  Kazuhito Kobayashi ,  Akiko Mimotogi ,  Chikaaki Kodama

IPC分类号： G06F17/50

CPC分类号： G03F1/70 ,  G03F1/84 ,  G03F7/70625

摘要： According to one embodiment, an original plate evaluation method is disclosed. The original plate includes a substrate and N patterns differing from one another in shape. The method includes selecting N1 patterns from the N patterns based on first criterion, obtaining measured values for the N1 patterns, performing a decision whether the obtained measured values satisfy first specification value, selecting N2 patterns from the N patterns based on second criterion, predicting shapes of transfer patterns corresponding to N2 patterns, performing a decision whether the predicted shapes satisfy second specification value, and evaluating the plate based on the decision.

摘要翻译： 根据一个实施例，公开了原版评估方法。 原版包括基板和N形图案，其形状彼此不同。 该方法包括基于第一准则从N个图案中选择N1个图案，获得N1个图案的测量值，执行所获得的测量值是否满足第一指定值，根据第二准则从N个图案中选择N2个图案，预测形状 对应于N2图案的传送图案，执行预测形状是否满足第二规格值的判定，以及基于该判定来评估印版。

公开(公告)号：US20120047475A1

公开(公告)日：2012-02-23

申请号：US13285650

申请日：2011-10-31

申请人： Toshiya Kotani

发明人： Toshiya Kotani

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  H01J2237/31769

摘要： A semiconductor device is provided having a physical pattern based on a designed pattern, the designed pattern including a target pattern and a correction pattern designed for a pattern to be formed on a wafer; the target pattern includes a first portion of an edge with a first distance, a second portion of the edge with a second distance, which is different from the first distance, and a third portion of the edge having a first region of the edge with the first distance and a second region of the edge with the second distance; and the correction pattern is added to at least one of the first portion, the second portion, and the third portion such that the first portion, the second portion, and the third portion are caused to differ from one another in dimensions of the designed pattern.

摘要翻译： 提供具有基于设计图案的物理图案的半导体器件，所设计的图案包括针对要在晶片上形成的图案设计的目标图案和校正图案; 目标图案包括具有第一距离的边缘的第一部分，具有第二距离的边缘的第二部分，其不同于第一距离，并且边缘的第三部分具有边缘的第一区域，其具有 第一距离和具有第二距离的边缘的第二区域; 并且将修正图案添加到第一部分，第二部分和第三部分中的至少一个，使得第一部分，第二部分和第三部分在设计图案的尺寸上彼此不同 。

公开(公告)号：US08112167B2

公开(公告)日：2012-02-07

申请号：US12354574

申请日：2009-01-15

申请人： Ayako Endo ,  Kenji Yoshida ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Ayako Endo ,  Kenji Yoshida ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F19/00 ,  G06F17/50

CPC分类号： G05B19/41865 ,  G05B19/41885 ,  H01L22/20 ,  H01L2924/0002 ,  Y02P90/20 ,  Y02P90/26 ,  H01L2924/00

摘要： A process control method comprises adjusting a process condition in consideration of a performance variation among a plurality of manufacturing apparatuses, the performance variation affecting a finished shape of a pattern used to manufacture a semiconductor device, running a simulation of the finished shape under the adjusted process condition, extracting a dangerous point of the pattern affecting satisfaction from the result of the simulation, comparing a first process capability serving as a judgment standard to find whether a production schedule of the device is achieved with a second capability serving to form a dangerous pattern containing the dangerous point, and improving the second process when the second process capability is lower than the first process capability.

摘要翻译： 一种过程控制方法包括考虑多个制造装置之间的性能变化来调整工艺条件，影响用于制造半导体器件的图案的成品形状的性能变化，在调整过程下运行成品形状的模拟 从模拟结果中提取影响满意度的模式的危险点，比较作为判断标准的第一处理能力，以确定是否实现具有第二能力的设备的生产计划，以形成含有 危险点，并且当第二处理能力低于第一处理能力时，改进第二过程。

公开(公告)号：US08101516B2

公开(公告)日：2012-01-24

申请号：US11857275

申请日：2007-09-18

申请人： Toshiya Kotani ,  Hiroko Nakamura ,  Koji Hashimoto

发明人： Toshiya Kotani ,  Hiroko Nakamura ,  Koji Hashimoto

IPC分类号： H01L21/4763

CPC分类号： H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

摘要： A block film is formed on a region which includes a region of an insulating layer where a first hole is to be formed, and in which no second hole is to be formed, and a resist film having openings for forming the first and second holes is formed on the block film and insulating layer. Etching is performed by using the resist film as a mask, thereby forming the first hole in the block film and insulating layer, and the second hole in the insulating layer. The depth of the first hole from the upper surface of the insulating layer is smaller than that of the second hole, so the first hole does not reach the semiconductor substrate.

摘要翻译： 在包括要形成第一孔的绝缘层的区域，并且不形成第二孔的区域上形成阻挡膜，并且具有用于形成第一孔和第二孔的开口的抗蚀剂膜是 形成在阻挡膜和绝缘层上。 通过使用抗蚀剂膜作为掩模进行蚀刻，从而在阻挡膜和绝缘层中形成第一孔，并在绝缘层中形成第二孔。 绝缘层的上表面的第一孔的深度小于第二孔的深度，所以第一孔不到达半导体衬底。

公开(公告)号：US07996794B2

公开(公告)日：2011-08-09

申请号：US11945697

申请日：2007-11-27

申请人： Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

发明人： Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Disclosed is a mask data processing method of correcting a hierarchical structure. In the case that in design data having a hierarchical structure including a plurality of cells each having a design pattern, when the total number of graphic forms or the total edge length of a design pattern on which the calculation of mask data processing is to be executed, the amount of calculation to be executed, or the expansion degree presumably becomes equal to or larger than a predetermined threshold value if the calculation of the mask data processing is executed on the design data having the initial hierarchical structure, the hierarchical structure is corrected. This correction is performed to reduce the total number of graphic forms or the total edge length of the design pattern on which the calculation is to be executed, the amount of calculation to be executed, of the expansion degree.

摘要翻译： 公开了一种校正层次结构的掩模数据处理方法。 在具有包括多个单元的设计数据的设计数据中，每个单元均具有设计图案时，当要执行掩模数据处理的计算的设计图案的总数或总边沿长度时 如果对具有初始层次结构的设计数据执行掩模数据处理的计算，则修正了要执行的计算量或扩展度等于或大于预定阈值等于或大于预定阈值。 执行该校正以减少要执行计算的设计模式的总数或总边缘长度，即要执行的计算量，扩展度。

公开(公告)号：US20100202181A1

公开(公告)日：2010-08-12

申请号：US12561531

申请日：2009-09-17

申请人： Takaki HASHIMOTO ,  Hidefumi Mukai ,  Yasunobu Kai ,  Toshiya Kotani

发明人： Takaki HASHIMOTO ,  Hidefumi Mukai ,  Yasunobu Kai ,  Toshiya Kotani

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C5/025

摘要： A semiconductor memory device includes a semiconductor substrate on which memory cells are formed. Interconnects are arranged along a first direction above the semiconductor substrate, and have regular intervals along a second direction perpendicular to the first direction. Interconnect contacts connect the interconnects and the semiconductor substrate, are arranged on three or more rows. The center of each of two of the interconnect contacts which are connected to the interconnects adjacent in the second direction deviate from each other along the first direction.

摘要翻译： 半导体存储器件包括形成有存储单元的半导体衬底。 互连件沿着半导体衬底上方的第一方向布置，并且沿着垂直于第一方向的第二方向具有规则的间隔。 互连触点连接互连和半导体衬底，布置在三行或更多行上。 连接到在第二方向相邻的互连件的两个互连触点中的每一个的中心沿着第一方向彼此偏离。

公开(公告)号：US20100082144A1

公开(公告)日：2010-04-01

申请号：US12554495

申请日：2009-09-04

申请人： Masanori TAKAHASHI ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Masanori TAKAHASHI ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F19/00 ,  G06F17/50

CPC分类号： G06F17/5081

摘要： Method of calculating pattern-failure-occurrence-region comprising calculating a pattern failure occurrence region using relation information and a layout used for forming a convex section, the relation information being a relation between a distance from a formed pattern in a film to cover the convex section on a substrate to the convex section and a region in the film in which a shape of the formed pattern cannot satisfy a predetermined condition because of influence of the convex section.

摘要翻译： 计算图案故障发生区域的方法包括使用关系信息和用于形成凸部的布局来计算图案故障发生区域，所述关系信息是从胶片中形成的图案到覆盖凸起的距离之间的关系 由于凸部的影响，形成图案的形状不能满足规定条件的膜中的与凸部的基板上的区域。

公开(公告)号：US07631287B2

公开(公告)日：2009-12-08

申请号：US11727288

申请日：2007-03-26

申请人： Kyoko Izuha ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Kyoko Izuha ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G03F7/705

摘要： A method in which a desired pattern is compared with a finish pattern to be formed on a wafer, which is predicted from a design pattern, based on a calculation of a light beam intensity, and a deviation quantity of the finish pattern from the desired pattern at each edge of the finish pattern and the desired pattern is calculated, comprising setting a reference light beam intensity for setting the desired pattern on a wafer, setting an evaluation point for comparison of the finish pattern with the desired pattern, calculating a light beam intensity at the evaluation point, calculating a differentiation value of the light beam intensity at the evaluation point, calculating an intersection of the differentiation value with the reference light beam intensity, and calculating a difference between the intersection and the evaluation point, the difference defining an edge deviation quantity of the finish pattern from the desired pattern.

摘要翻译： 将期望图案与根据设计图案预测的要在晶片上形成的光洁度图案进行比较的方法，基于光束强度的计算和完成图案与期望图案的偏差量 在完成图案的每个边缘处并计算所需图案，包括设置用于在晶片上设置期望图案的参考光束强度，设置用于将完成图案与期望图案进行比较的评估点，计算光束强度 在评价点，计算评价点的光束强度的微分值，计算微分值与参考光束强度的交点，计算交点与评价点之间的差，限定边缘的差 完成图案与期望图案的偏差量。

公开(公告)号：US07585597B2

公开(公告)日：2009-09-08

申请号：US11259069

申请日：2005-10-27

申请人： Tadahito Fujisawa ,  Takeshi Ito ,  Toshiya Kotani

发明人： Tadahito Fujisawa ,  Takeshi Ito ,  Toshiya Kotani

IPC分类号： G03F1/00

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： A mask pattern data generating method is disclosed, which comprises preparing mask pattern data which corresponds to a design pattern including a pair of line patterns formed of two line patterns, and disposing an auxiliary pattern which is un-transferable to a resist film at a center of a space region between the pair of line patterns, in which the disposing of the auxiliary pattern includes obtaining a shape of the auxiliary pattern which meets formulae in which a width in the short edge direction of the auxiliary pattern, a space width between the auxiliary pattern and one of the pair of line patterns, a wavelength of an exposure light emitted by a projection aligner using a photo mask at exposure, and a numerical apertures of a projection lens of the projection aligner are defined as parameters, and disposing the obtained auxiliary pattern at the center of the space region.

摘要翻译： 公开了一种掩模图案数据生成方法，其包括制备对应于包括由两条线图案形成的一对线图案的设计图案的掩模图案数据，并且将不可转印到辅助图案的抗蚀剂膜设置在中心 在一对线图案之间的空间区域中，其中辅助图案的设置包括获得辅助图案的形状，其满足辅助图案的短边方向上的宽度，辅助图案的短边方向之间的空间宽度 图案和一对线图案中的一个，曝光时由使用光掩模的投影对准器发射的曝光光的波长和投影对准器的投影透镜的数值孔径被定义为参数，并且将所获得的辅助 模式在空间区域的中心。