公开(公告)号：US08054319B2

公开(公告)日：2011-11-08

申请号：US12487198

申请日：2009-06-18

申请人： Kwang-Kee Lee ,  Jong-Ho Lee ,  Sung-Wook Byun ,  Un-Gyo Jung ,  Glenn A. Adams

发明人： Kwang-Kee Lee ,  Jong-Ho Lee ,  Sung-Wook Byun ,  Un-Gyo Jung ,  Glenn A. Adams

IPC分类号： G09G5/00 ,  H04N9/74 ,  H04N5/445 ,  G06F3/00 ,  G06F13/00

CPC分类号： H04N5/45 ,  H04N21/4316 ,  H04N21/43615 ,  H04N21/4433 ,  H04N21/4622

摘要： The present invention performs multiscreen configuration and multiscreen management by using a plurality of screens and a plurality of methods in order to represent a plurality of service contents. In accordance with a multiscreen configuration method of the present invention, by mutually assigning one or more broadcasting services, one or more logical screens, one or more display screens, and one or more output ports, ultimately outputting service contents which are executed on screens assigned by output ports, and setting, changing, and reporting configuration of a multiscreen, the configuration of the multiscreen may be set or reset so as to effectively output various service contents on the multiscreen by using a desired method.

摘要翻译： 本发明通过使用多个屏幕和多种方法来执行多屏幕配置和多屏幕管理，以便表示多个服务内容。 根据本发明的多屏配置方法，通过相互分配一个或多个广播服务，一个或多个逻辑屏幕，一个或多个显示屏幕和一个或多个输出端口，最终输出在分配的屏幕上执行的服务内容 通过输出端口以及多屏幕的设置，改变和报告配置，可以设置或重置多画面的配置，以便通过使用期望的方法在多画面上有效地输出各种服务内容。

公开(公告)号：US20110254076A1

公开(公告)日：2011-10-20

申请号：US13055881

申请日：2008-05-08

申请人： Jong-Ho Lee

发明人： Jong-Ho Lee

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0483 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/8616

摘要： Provided is an ultra highly-integrated flash memory cell device. The cell device includes a semiconductor substrate, a first doping semiconductor area formed on the semiconductor substrate, a second doping semiconductor area formed on the first doping semiconductor area, and a tunneling insulating layer, a charge storage node, a control insulating layer, and a control electrode which are sequentially formed on the second doping semiconductor area. The first and second doping semiconductor areas are doped with impurities of the different semiconductor types According to the present invention, it is possible to greatly improve miniaturization characteristics and performance of the cell devices in conventional NOR or NAND flash memories. Unlike conventional transistor type cell devices, the cell device according to the present invention does not have a channel and a source/drain. Therefore, in comparison with the conventional memories, the fabricating process can be simplified, and the problem such as cross-talk or read disturb can be greatly reduced.

摘要翻译： 提供了一种超高度集成的闪存单元设备。 电池器件包括半导体衬底，形成在半导体衬底上的第一掺杂半导体区域，形成在第一掺杂半导体区域上的第二掺杂半导体区域，以及隧穿绝缘层，电荷存储节点，控制绝缘层和 控制电极依次形成在第二掺杂半导体区域上。 第一掺杂半导体区域和第二掺杂半导体区域掺杂有不同半导体类型的杂质根据本发明，可以大大提高常规NOR或NAND闪存中的单元装置的小型化特性和性能。 与传统晶体管型电池器件不同，根据本发明的电池器件不具有沟道和源极/漏极。 因此，与常规存储器相比，可以简化制造过程，并且可以大大减少串扰或读取干扰等问题。

公开(公告)号：US20110244634A1

公开(公告)日：2011-10-06

申请号：US13103553

申请日：2011-05-09

申请人： Young-Lyong Kim ,  Jong-Ho Lee ,  Cheul-Joong Youn ,  Eun-Chul Ahn

发明人： Young-Lyong Kim ,  Jong-Ho Lee ,  Cheul-Joong Youn ,  Eun-Chul Ahn

IPC分类号： H01L21/56

CPC分类号： H01L25/105 ,  H01L24/73 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package includes a first package that a first semiconductor chip is mounted on a front side of a first substrate and a redistributed pad including a first redistributed pad electrically connected to the first substrate and a second redistributed pad electrically connected to the first redistributed pad is disposed on the first semiconductor chip and a second package that a second semiconductor chip is mounted on a front side of a second substrate, the second package including a connection member electrically connected to the second redistributed pad. The connection member electrically connected to the redistributed pad electrically connects the first and second packages to each other.

摘要翻译： 半导体封装以及半导体封装的制造方法。 半导体封装包括第一封装，第一半导体芯片安装在第一基板的前侧，以及重新分布的焊盘，其包括电连接到第一基板的第一再分布焊盘和电连接到第一再分布焊盘的第二再分布焊盘 设置在第一半导体芯片上的第二封装以及第二半导体芯片安装在第二基板的正面上的第二封装，所述第二封装包括与第二再分布焊盘电连接的连接部件。 电连接到再分布垫的连接构件将第一和第二封装彼此电连接。

公开(公告)号：US08013402B2

公开(公告)日：2011-09-06

申请号：US12574912

申请日：2009-10-07

申请人： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

发明人： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

IPC分类号： H01L21/02

CPC分类号： H01L21/28185 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

摘要： Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

摘要翻译： 提供了在通道区​​域上包括多层电介质膜的晶体管。 多层电介质包括下电介质膜，该电介质膜的厚度至少为多层电介质膜的厚度的50％，并且包括金属氧化物，金属硅酸盐，铝酸盐或其混合物，以及上电介质膜 在下介电膜上，上电介质膜包含III族金属氧化物，III族金属氮化物，第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。 在多层电介质膜上设置栅电极。

公开(公告)号：US08008771B2

公开(公告)日：2011-08-30

申请号：US12193561

申请日：2008-08-18

申请人： Pyoung-Wan Kim ,  Eun-Chul Ahn ,  Jong-Ho Lee ,  Teak-Hoon Lee ,  Chul-Yong Jang

发明人： Pyoung-Wan Kim ,  Eun-Chul Ahn ,  Jong-Ho Lee ,  Teak-Hoon Lee ,  Chul-Yong Jang

IPC分类号： H01L23/48

CPC分类号： H01L23/49816 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.

摘要翻译： 一种半导体芯片封装，包括：半导体芯片，包括具有接合焊盘的第一表面，与所述第一表面相对的第二表面和侧壁; 围绕半导体芯片的第二表面和侧壁的成型延伸部分; 重新分布图案从接合焊盘延伸到模制延伸部分上，并且电连接到焊盘; 碰撞焊球上的再分布图案; 以及模制层，其被配置为覆盖半导体芯片的第一表面和模制延伸部分，同时暴露每个凸块焊球的部分。 成型层在彼此相邻的凸块焊料球之间具有凹面弯月面。

公开(公告)号：US07960778B2

公开(公告)日：2011-06-14

申请号：US12314163

申请日：2008-12-05

申请人： Jong-Ho Lee

发明人： Jong-Ho Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/792

摘要： The present invention relates to a flash memory cell string. The flash memory cell string includes a plurality of cell devices and switching devices connected to ends of the cell devices. Each of the cell devices includes a semiconductor substrate, and a transmissive insulating layer, a charge storage node, a control insulating layer and a control electrode sequentially formed on the semiconductor substrate. In the flash memory cell string, a buried insulating layer is provided on the semiconductor substrate between the cell device and an adjacent cell device, thus enabling an inversion layer, which performs the functions of source/drain, to be easily formed.According to the present invention, the reduction characteristics and performance of the cell devices of NAND flash memory are improved, and the inversion layer of a channel is induced through fringing electric fields from the control electrode and the charge storage node if necessary.

摘要翻译： 本发明涉及闪存单元串。 闪存单元串包括连接到单元设备的端部的多个单元设备和交换设备。 每个电池器件包括依次形成在半导体衬底上的半导体衬底和透射绝缘层，电荷存储节点，控制绝缘层和控制电极。 在闪速存储单元串中，在单元装置与相邻单元装置之间的半导体基板上设置掩埋绝缘层，能够容易地形成执行源/漏功能的反转层。 根据本发明，NAND闪存的单元装置的还原特性和性能得到改善，如果需要，通过来自控制电极和电荷存储节点的边缘电场来感应通道的反转层。

公开(公告)号：US20100219929A1

公开(公告)日：2010-09-02

申请号：US12738016

申请日：2008-10-14

申请人： Jong-Ho Lee

发明人： Jong-Ho Lee

IPC分类号： H01H85/02

CPC分类号： H01H37/765

摘要： Disclosed is a thermal fuse structured in such a manner that a resistance heating element which generates heat according to an electric current is mounted within a case charged with a solid fusible material so that the fusible material is liquefied by heat of the resistance heating element caused by the external temperature and also by the current applied to a circuit, accordingly disconnecting the circuit. Since the resistance heating element is integrally formed in the case, the thermal fuse is capable of functioning as both a thermal fuse and a current fuse, disconnecting the circuit by both the external heat and the overcurrent. Especially, when the resistance heating element comprises a positive thermal coefficient (PTC) element capable of temperature measurement, the current flowing through the circuit can be measured.

摘要翻译： 公开了一种热熔丝，其结构使得根据电流产生热量的电阻加热元件安装在装有固体可熔材料的壳体内，使得易熔材料由于电阻加热元件的热​​量而液化，由 外部温度以及施加到电路的电流，从而断开电路。 由于电阻加热元件在壳体中整体形成，所以热熔丝能够用作热熔丝和电流保险丝，同时通过外部热和过电流来断开电路。 特别地，当电阻加热元件包括能够进行温度测量的正热系数（PTC）元件时，可以测量流过电路的电流。

公开(公告)号：US07767512B2

公开(公告)日：2010-08-03

申请号：US12019449

申请日：2008-01-24

申请人： Hyung-Suk Jung ,  Jong-Ho Lee ,  Sung-Kee Han ,  Yun-Ki Choi ,  Ha Jin Lim

发明人： Hyung-Suk Jung ,  Jong-Ho Lee ,  Sung-Kee Han ,  Yun-Ki Choi ,  Ha Jin Lim

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28026 ,  H01L29/49

摘要： In a method of manufacturing a semiconductor device, a gate insulation layer is formed on a substrate including a first channel of a first conductive type and a second channel of a second conductive type different from the first conductive type. A first conductive layer including a first metal is formed on the gate insulation layer, and a second conductive layer including a second metal different from the first metal is formed on the first conductive layer formed over the second channel. The second conductive layer is partially removed by a wet etching process to form a second conductive layer pattern over the second channel.

摘要翻译： 在制造半导体器件的方法中，在包括第一导电类型的第一沟道和不同于第一导电类型的第二导电类型的第二沟道的衬底上形成栅极绝缘层。 在栅极绝缘层上形成包括第一金属的第一导电层，并且在形成在第二沟道上的第一导电层上形成包括不同于第一金属的第二金属的第二导电层。 通过湿式蚀刻工艺部分去除第二导电层，以在第二通道上形成第二导电层图案。

公开(公告)号：US20100163947A1

公开(公告)日：2010-07-01

申请号：US12632115

申请日：2009-12-07

申请人： Jong-Ho Lee

发明人： Jong-Ho Lee

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L27/0629 ,  H01L27/0682 ,  H01L28/20 ,  H01L28/40

摘要： A PIP capacitor and methods thereof. A method of fabricating a PIP capacitor may include forming a field oxide film over a silicon substrate to define a device isolating region and/or an active region. A method of fabricating a PIP capacitor may include forming a lower polysilicon electrode having doped impurities on and/or over an field oxide film. A method of fabricating a PIP capacitor may include performing an oxidizing step to form a first oxide film over a polysilicon and/or a second oxide film on and/or over an active region. A method of fabricating a PIP capacitor may include forming an upper polysilicon electrode on and/or over a region of a first oxide film and forming a gate electrode on and/or over a second oxide film at substantially the same time. A method of fabricating a PIP capacitor may include forming a polysilicon resistor. A PIP capacitor is disclosed.

摘要翻译： 一种PIP电容器及其方法。 制造PIP电容器的方法可以包括在硅衬底上形成场氧化物膜以限定器件隔离区和/或有源区。 制造PIP电容器的方法可以包括在场氧化物膜上形成具有掺杂杂质的下部多晶硅电极。 制造PIP电容器的方法可以包括执行氧化步骤以在活性区上和/或上方在多晶硅和/或第二氧化物膜上形成第一氧化膜。 制造PIP电容器的方法可以包括在第一氧化物膜的区域上和/或上方形成上部多晶硅电极，并且在基本上同时在第二氧化膜上形成和/或在第二氧化物膜上形成栅电极。 制造PIP电容器的方法可以包括形成多晶硅电阻器。 公开了一种PIP电容器。

公开(公告)号：US20100102372A1

公开(公告)日：2010-04-29

申请号：US12200929

申请日：2008-08-28

申请人： Jong-Ho Lee ,  Ki-Heung Park

发明人： Jong-Ho Lee ,  Ki-Heung Park

IPC分类号： H01L27/108 ,  H01L21/84

CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

摘要： Provided are a high-performance one-transistor floating-body DRAM cell device and a manufacturing method thereof. The one-transistor floating-body DRAM cell device includes: a semiconductor substrate; a gate stack which is formed on the semiconductor substrate; a control electrode which is formed on the semiconductor substrate and surrounded by the gate stack; a floating body which is formed on the control electrode that is surrounded by the gate stack; source/drain which are formed at left and right sides of the floating body; an insulating layer which insulates the source/drain from the semiconductor substrate and the control electrode; a gate insulating layer which is formed on the floating body and the source/drain; and a gate electrode which is formed on the gate insulating layer. In the cell device having a double-gate structure, charges can be stored in a non-volatile manner by the control electrodes, so that it is possible to improve a degree of integration of devices, a uniformity of characteristic, and a sensing margin.

摘要翻译： 提供一种高性能单晶体体浮体DRAM单元装置及其制造方法。 单晶体体浮体DRAM单元装置包括：半导体基板; 形成在所述半导体基板上的栅极叠层; 控制电极，其形成在所述半导体基板上并被所述栅极堆叠包围; 浮动体，其形成在所述控制电极上，所述浮体被所述栅极叠层包围; 在浮体的左侧和右侧形成的源极/漏极; 绝缘层，其使源极/漏极与半导体衬底和控制电极绝缘; 形成在浮体和源极/漏极上的栅极绝缘层; 以及形成在栅极绝缘层上的栅电极。 在具有双栅极结构的电池装置中，可以通过控制电极以非易失性的方式存储电荷，使得可以提高器件的集成度，特性的均匀性和感测裕度。