公开(公告)号：US06473865B1

公开(公告)日：2002-10-29

申请号：US09272171

申请日：1999-03-18

申请人： Masahiro Kamoshida ,  Haruki Toda ,  Tsuneaki Fuse ,  Yukihito Oowaki

发明人： Masahiro Kamoshida ,  Haruki Toda ,  Tsuneaki Fuse ,  Yukihito Oowaki

IPC分类号： G06F112

CPC分类号： G06F1/3287 ,  G06F1/10 ,  G06F1/3203 ,  Y02D10/126 ,  Y02D10/171

摘要： Each delay unit is divided into two delay unit groups, the preceding stage side and the succeeding stage side. To the delay unit group in the preceding stage side, power supply voltage is supplied via a power supply terminal, and to each delay unit of the delay unit group in the succeeding stage side, power supply voltage is supplied from the power supply terminal via a power supply control switch. A forward-pulse detecting circuit detects that forward pulse was propagated to a stage between the N-th stage and a stage a predetermined number of stages before the N-th, and outputs the detected result to the power supply control switch. With this operation, when forward pulse is propagated to the (N+1)th stage, power supply voltage is supplied also to the delay unit group in the succeeding stage side. As electric power is not supplied to the delay unit group in the succeeding stage side when forward pulse is not propagated to the (N+1)th stage, wasteful consumption of electric power is prevented.

摘要翻译： 每个延迟单元被分成两个延迟单元组，即前级侧和后级侧。 对于前级侧的延迟单元组，经由电源端子向后级侧的延迟单元组的延迟单元供给电源电压，经由电源端子从电源端子供给电源电压 电源控制开关。 正向脉冲检测电路检测正向脉冲传播到第N级的第N级与预定级的级之间的级，并将检测结果输出到电源控制开关。 通过这种操作，当正向脉冲传播到第（N + 1）级时，电源电压也被提供给后级侧的延迟单元组。 当正向脉冲不传播到第（N + 1）级时，由于不向后级侧的延迟单元组提供电力，所以防止了浪费的电力消耗。

公开(公告)号：US06393080B1

公开(公告)日：2002-05-21

申请号：US09271329

申请日：1999-03-18

申请人： Masahiro Kamoshida ,  Haruki Toda ,  Tsuneaki Fuse ,  Yukihito Oowaki

发明人： Masahiro Kamoshida ,  Haruki Toda ,  Tsuneaki Fuse ,  Yukihito Oowaki

IPC分类号： H04L700

CPC分类号： G11C7/222 ,  G11C7/22 ,  H03K5/135 ,  H03L7/00 ,  H04L7/0337

摘要： A state-holding circuit initializing circuit initializes state-holding circuit when propagation of forward pulse to the forward-pulse delay circuits in the last stage is detected. With this operation, synchronization is established in a short time from the resumption of outputting from a receiver. The state-holding circuit control circuit also controls the reset timing of the state-holding circuit. A forward-pulse adjusting circuit controls the pulse width of forward pulse to be supplied to the forward-pulse delay line. With this operation, the stages from the stage where rearward pulse was generated to the first stage are securely turned to the set state, enabling propagation of rearward pulse and synchronization is established. Thus, synchronization is established reliably even when output from a receiver stops or the duty of an external clock signal is heavy.

摘要翻译： 状态保持电路初始化电路在正向脉冲传播到最后一级的正向脉冲延迟电路时，初始化状态保持电路。 通过该操作，从恢复从接收器输出的短时间内建立同步。 状态保持电路控制电路还控制状态保持电路的复位定时。 正向脉冲调整电路控制要提供给正向脉冲延迟线的正向脉冲的脉冲宽度。 通过该动作，从产生向后脉冲的阶段到第一阶段的阶段被牢固地转到设定状态，从而能够建立向后脉冲的传播和同步。 因此，即使从接收器的输出停止或外部时钟信号的占空比很重，也能够可靠地建立同步。

公开(公告)号：US06389521B1

公开(公告)日：2002-05-14

申请号：US09655939

申请日：2000-09-06

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G06F1202

CPC分类号： G11C11/4096 ,  G11C7/1075

摘要： An image memory has a random access memory array capable of being randomly accessed; a serial access memory array partitioned into n power of 2 (n>1) divisional areas cyclically and serially accessed in asynchronism with the random access memory; data transfer unit for transferring data between the random access memory array and the serial access memory array; a determined unit for determining a row of data to be transferred from the random access memory array to each of the divisional areas; and a designating unit for designating at least one of a top serial access address and a last serial access address respectively of each divisional area, wherein the data transfer unit executes data transfer from the random access memory array to the serial access memory array in accordance with outputs from the determining unit and the designating unit.

摘要翻译： 图像存储器具有随机访问的随机存取存储器阵列; 串行访问存储器阵列，其被循环地和随机存取存储器不同步地循环地和串行访问地分成2（n> 1）个分区的n个功率; 数据传送单元，用于在随机存取存储器阵列和串行存取存储器阵列之间传送数据; 确定单元，用于确定要从所述随机存取存储器阵列传送到每个所述分区的数据行; 以及指定单元，用于分别指定每个分区的顶部串行访问地址和最后一个串行访问地址中的至少一个，其中数据传送单元执行从随机存取存储器阵列到串行访问存储器阵列的数据传送，根据 来自确定单元和指定单元的输出。

公开(公告)号：US06335904B1

公开(公告)日：2002-01-01

申请号：US09852037

申请日：2001-05-10

申请人： Kenji Tsuchida ,  Haruki Toda

发明人： Kenji Tsuchida ,  Haruki Toda

IPC分类号： G11C800

CPC分类号： G11C11/4094 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/22 ,  G11C2207/002

摘要： In a semiconductor memory system, an SDRAM comprises a memory cell array 101 which is divided into a plurality of cell array blocks, a column decoder, a row decoder, and a sense amplifier circuit. In the SDRAM, a first operation mode with a first cycle time is set when successive access within a cell array block is conducted, a second operation mode with a second cycle time shorter than the first cycle time is set when successive access covering the cell array blocks being apart from each other is conducted and a third operation mode with a medium cycle time is set when successive access covering the cell array blocks adjacent to each other is conducted. With the above constitution, a high speed access can be realized without provision of a specific accessory circuit while suppressing overhead for a semiconductor chip size.

摘要翻译： 在半导体存储器系统中，SDRAM包括被分成多个单元阵列块的存储单元阵列101，列解码器，行解码器和读出放大器电路。 在SDRAM中，当进行单元阵列块中的连续访问时，设置具有第一周期时间的第一操作模式，当覆盖单元阵列的连续访问时，设置具有比第一周期时间短的第二周期时间的第二操作模式 进行彼此分开的块，并且进行覆盖彼此相邻的单元阵列块的连续访问时，设定具有中等周期时间的第三操作模式。 利用上述结构，可以在不设置特定附件电路的同时抑制半导体芯片尺寸的开销，实现高速访问。

公开(公告)号：US06321343B1

公开(公告)日：2001-11-20

申请号：US09698635

申请日：2000-10-27

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G06F104

CPC分类号： G11C7/1093 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/225

摘要： A maximum flight time measuring circuit constituted by a first delay circuit for delaying a system clock and controlling its delay time in accordance with a strobe clock from DIMMs and a delayline register circuit for storing a delayed state in the delay circuit, and a second delay circuit are provided. Contents of the delayline register circuit are input to the second delay circuit, which is controlled to generate the same delay as that of the first delay circuit. The output of the second delay circuit is supplied as a data fetch signal to a control buffer for receiving read data DQ from the DIMMs.

摘要翻译： 一种最大飞行时间测量电路，由第一延迟电路构成，用于根据来自DIMM的选通时钟延迟系统时钟并控制其延迟时间;以及延迟线寄存器电路，用于在延迟电路中存储延迟状态;以及第二延迟电路 被提供。 延迟线寄存器电路的内容被输入到第二延迟电路，其被控制以产生与第一延迟电路相同的延迟。 第二延迟电路的输出作为数据提取信号提供给用于从DIMM接收读取数据DQ的控制缓冲器。

公开(公告)号：US06310821B1

公开(公告)日：2001-10-30

申请号：US09435627

申请日：1999-11-08

申请人： Haruki Toda ,  Hitoshi Kuyama

发明人： Haruki Toda ,  Hitoshi Kuyama

IPC分类号： G11C800

CPC分类号： G11C8/04 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2207/2254

摘要： A clock-synchronous semiconductor memory device includes many memory cells arranged in matrix, a count section for counting the actual number of cycles of a continuous, externally-supplied basic clock signal, a control section for inputting a row enable control signal (/RE) and the column enable control signal (/CE) provided from an external device, other than the basic clock signal, for which the control signals are at a specified level, synchronized with the basic control signal, and for setting the initial address for data access of the memory cells, and a data I/O section for executing a data access operation for the address set by the control section. In the device, the output of data from the memory cells through the data I/O means is started after the setting of the initial address by the control sections and after a specified number of basic clock signals has been counted by the count section.

摘要翻译： 时钟同步半导体存储器件包括以矩阵形式布置的许多存储器单元，用于对连续的外部供给的基本时钟信号的实际循环次数进行计数的计数部分，用于输入行使能控制信号（/ RE）的控制部分， 以及与基本时钟信号不同的外部设备提供的与基本控制信号同步的指令级别的列使能控制信号（/ CE），并且用于设置用于数据访问的初始地址 以及用于执行由控制部分设置的地址的数据访问操作的数据I / O部分。 在该设备中，通过控制部分设置初始地址之后并且在计数部分计数了指定数量的基本时钟信号之后，通过数据I / O装置从存储器单元输出数据。

公开(公告)号：US06285623B1

公开(公告)日：2001-09-04

申请号：US09328562

申请日：1999-06-09

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C800

CPC分类号： G11C7/1051 ,  G11C5/025 ,  G11C7/10 ,  G11C7/18 ,  G11C29/12

摘要： Banks are arranged on a memory chip, forming a matrix. A data input/output circuit is provided at one side of the memory chip. A data bus is provided among the banks and connected to the data input/output circuit. Each bank has a plurality of memory cell arrays a cell-array controller, a row decoder, column decoders, and a DQ buffer. The cell-array controller and the row decoder oppose each other. The column decoders oppose the DQ buffer. Local DQ lines are provided between the memory cell arrays, and global DQ liens extend over the memory cell arrays. The local DQ lines extend at right angles to the global DQ lines.

摘要翻译： 银行被布置在存储芯片上，形成矩阵。 数据输入/输出电路设置在存储芯片的一侧。 一个数据总线被提供在各个存储体之间并连接到数据输入/输出电路。 每个存储体具有多个存储单元阵列，单元阵列控制器，行解码器，列解码器和DQ缓冲器。 单元阵列控制器和行解码器彼此相对。 列解码器与DQ缓冲区相对。 在存储单元阵列之间提供局部DQ线，并且全局DQ留置线延伸到存储器单元阵列上。 局部DQ线与全局DQ线成直角延伸。

公开(公告)号：US06219295B1

公开(公告)日：2001-04-17

申请号：US09526349

申请日：2000-03-16

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C800

CPC分类号： G11C5/025 ,  G11C7/10

摘要： A plurality of sense amplifiers are provided between a plurality of memory cell arrays having a plurality of memory cells. These sense amplifiers are connected to bit lines of the respective memory cell arrays by array selection switches. Each of the sense amplifiers is connected to data lines by column switches. An array control portion is provided at each of the memory cell arrays. This array control portion selectively controls the array selection switches and column switches to transmit the data in an arbitrary memory cell in a memory cell array to the data lines through the sense amplifier.

摘要翻译： 在具有多个存储单元的多个存储单元阵列之间提供多个读出放大器。 这些读出放大器通过阵列选择开关连接到各个存储单元阵列的位线。 每个读出放大器通过列开关连接到数据线。 在每个存储单元阵列中设置阵列控制部分。 该阵列控制部分选择性地控制阵列选择开关和列开关，以通过读出放大器将存储单元阵列中的任意存储单元中的数据传输到数据线。

公开(公告)号：US6144615A

公开(公告)日：2000-11-07

申请号：US418958

申请日：1999-10-14

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C7/10 ,  G11C11/4096 ,  G11C7/103 ,  G11C7/1072

摘要： A synchronous DRAM has cell arrays arranged in matrix, divided into banks accessed asynchronously, and n bit I/O buses for transferring data among the cell arrays. In the DRAM, the banks are divided into m blocks, the n-bit I/O buses located between adjacent banks, is used for time sharing between adjacent banks in common, the n bit I/O buses, used for time sharing between adjacent banks in common, are grouped into n/m-bit I/O buses, every n/m bits for each block of m blocks of bank, and in each block in each bank, data input/output are carried out between the n/m-bit I/O buses and data bus lines in each block. A synchronous DRAM includes a first and second internal clock systems for controlling a burst data transfer in which a string of burst data being transferred in synchronism with an external clock signal, when one of the internal clock systems is driven, the burst data transfer is commenced immediately by the selected internal clock system.

公开(公告)号：US6014335A

公开(公告)日：2000-01-11

申请号：US326948

申请日：1999-06-07

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C29/04 ,  G11C7/00 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00

CPC分类号： G11C29/785 ,  G11C29/808 ,  G11C29/846

摘要： It is an object of this invention to provide a semiconductor memory device in which a failure can be efficiently remedied even for a larger number of bits. In a multi-bit memory capable of simultaneously exchanging a plurality of data upon reception of an address, spare DQ lines (15c) commonly used for each I/O, a spare sense amplifier circuit (13c), a spare column switch (14c), a fuse box (20) for storing the address of a DQ line in which a failure has occurred, and fuse circuits (21-1, 21-2, . . . ) for storing an I/O to which the failure-DQ line belongs are arranged to remedy the failure for each I/O. Since only a memory cell belonging to one I/O where a failure has occurred is replaced, unnecessary replacement is not executed, and the memory cell can be efficiently remedied even for a larger number of bits.

摘要翻译： 本发明的目的是提供一种半导体存储器件，其中即使对于较大数量的位也可有效地修复故障。 在能够在接收到地址时同时交换多个数据的多位存储器中，通常用于每个I / O的备用DQ线（15c），备用读出放大器电路（13c），备用列开关（14c） ，用于存储其中发生故障的DQ线的地址的保险丝盒（20）和用于存储故障DQ的I / O的熔丝电路（21-1,21-2 ...） 排列的行被排列以补救每个I / O的故障。 由于只有属于发生故障的一个I / O的存储单元被替换，所以不执行不必要的替换，并且即使对于较大数量的位也能够有效地补救存储单元。