公开(公告)号：US06970521B2

公开(公告)日：2005-11-29

申请号：US09741086

申请日：2000-12-21

申请人： Shiro Dosho

发明人： Shiro Dosho

IPC分类号： H03L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L25/40 ,  H04L27/06 ,  H03H11/16

CPC分类号： H04L7/0338 ,  H04L7/0025

摘要： A data extracting circuit extracts data much more accurately at a much higher response speed. A clock transfer section propagates an input clock signal through unit delay devices thereof. An edge detecting section locates an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal. In response to an edge detection signal indicating the clock signal edge located, a clock selecting section selects one of outputs of the delay devices, and presents the output as a clock input to a latch.

摘要翻译： 数据提取电路以更高的响应速度更准确地提取数据。 时钟传送部分通过其单位延迟装置传播输入时钟信号。 边沿检测部分将时钟信号的边缘定位在由输入数据信号的给定边缘表示的时间内，该边缘正在通过时钟传送部分传播。 响应于指示所述时钟信号边缘的边缘检测信号，时钟选择部分选择延迟器件的输出之一，并且将输出作为时钟输入呈现给锁存器。

公开(公告)号：US20050049809A1

公开(公告)日：2005-03-03

申请号：US10915345

申请日：2004-08-11

申请人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara

发明人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara

IPC分类号： G01R31/316 ,  G01R35/00 ,  G06F19/00

CPC分类号： G01R35/005 ,  G01R31/316

摘要： An analog circuit automatic calibration system for calibrating an object circuit that is an analog circuit having a characteristic changing with an input set value. The system includes: a set value storage section for storing a value and outputting the value to the object circuit as the set value; a characteristic detection section for detecting the characteristic of the object circuit; a first characteristic change section for determining the set value so that the characteristic of the object circuit is optimized; a second characteristic change section for updating the set value so that the characteristic of the object circuit is maintained, using an algorithm different from that used in the first characteristic change section; and a selector for selecting either one of the outputs of the first and second characteristic sections to enable the selected one to be stored in the set value storage section.

摘要翻译： 一种模拟电路自动校准系统，用于校准作为具有随着输入设定值变化的特性的模拟电路的目标电路。 该系统包括：设定值存储部分，用于存储值并将该值输出到对象电路作为设定值; 用于检测所述目标电路的特性的特性检测部分; 用于确定所述设定值使得所述对象电路的特性被优化的第一特征变化部分; 第二特征变化部，使用与第一特征变化部中使用的算法不同的算法来更新设定值，使得保持对象电路的特性; 以及选择器，用于选择第一和第二特征部分的输出之一，以使所选择的一个存储在设定值存储部分中。

公开(公告)号：US06801587B2

公开(公告)日：2004-10-05

申请号：US09741086

申请日：2000-12-21

申请人： Shiro Dosho

发明人： Shiro Dosho

IPC分类号： H04L2706

摘要： A data extracting circuit extracts data much more accurately at a much higher response speed. A clock transfer section propagates an input clock signal through unit delay devices thereof. An edge detecting section locates an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal. In response to an edge detection signal indicating the clock signal edge located, a clock selecting section selects one of outputs of the delay devices, and presents the output as a clock input to a latch.

公开(公告)号：US5828717A

公开(公告)日：1998-10-27

申请号：US624960

申请日：1996-03-27

申请人： Keiichi Kusumoto ,  Shiro Dosho ,  Yutaka Terada ,  Akira Matsuzawa

发明人： Keiichi Kusumoto ,  Shiro Dosho ,  Yutaka Terada ,  Akira Matsuzawa

IPC分类号： G01R29/027 ,  G01C21/00

CPC分类号： G01R29/0273

摘要： There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption. An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition. A time-difference operating circuit corrects the numeric data outputted from the signal converting circuit based on the number of circulations of signal transition outputted from the counter circuit to provide time data, while calculating and outputting the pulse spacing of the pulse signal to be measured.

摘要翻译： 提供了一种用于以高精度和低功耗测量脉冲信号的脉冲间隔的时间计数电路。 由连接在环上的奇数个反相器组成的逆变器环振荡，并且一个信号转换发生在似乎在逆变器环周围似乎循环。 连接到构成逆变器环的逆变器的各个输出端子的保持电路在待测脉冲信号的上升沿同时输出从逆变器输出的信号。 然后，输出的信号由信号转换电路转换成数字数据。 连接到构成逆变器环的逆变器之一的输出端的计数器电路对信号转换的循环数进行计数。 时差操作电路根据从计数器电路输出的信号转换的循环数来校正从信号转换电路输出的数字数据，以提供时间数据，同时计算并输出要测量的脉冲信号的脉冲间隔。

公开(公告)号：US5822236A

公开(公告)日：1998-10-13

申请号：US863209

申请日：1997-05-27

申请人： Shiro Dosho ,  Hidehiko Kurimoto ,  Naoshi Yanagisawa

发明人： Shiro Dosho ,  Hidehiko Kurimoto ,  Naoshi Yanagisawa

IPC分类号： G11C27/00 ,  G11C27/04 ,  H03H19/00 ,  H04N9/78

CPC分类号： G11C27/04 ,  G11C27/00 ,  H03H19/004 ,  H04N9/78

摘要： The invention provides an analog FIFO memory from which a written analog signal can be accurately read by eliminating errors in the analog signal between the write operation and the read operation. Prior to the read operation for reading the analog signal from a memory cell through a memory bus, a reset operation for setting the memory bus at a predetermined potential is conducted so as to remove a charge stored in a parasitic capacitance of the memory bus. The input terminal of a read circuit is set at a predetermined potential, with a write circuit disconnected from the memory bus by using an input circuit and with the read circuit connected with the memory bus by using an output circuit. In this manner, the memory bus is set at the predetermined potential, and the charge stored in the parasitic capacitance is discharged. At this point, a switch in each memory cell is in an off-state, and hence, a charge corresponding to the analog signal can be retained in the memory cell.

摘要翻译： 本发明提供了一种模拟FIFO存储器，通过消除写入操作和读取操作之间的模拟信号中的错误，可以准确地读取写入的模拟信号。 在从存储器单元通过存储器总线读取模拟信号的读取操作之前，进行用于将存储器总线设置在预定电位的复位操作，以便消除存储在存储器总线的寄生电容中的电荷。 读取电路的输入端子通过使用输入电路和与存储器总线连接的读取电路通过使用输出电路将写入电路从存储器总线断开而被设置在预定电位。 以这种方式，将存储器总线设置在预定电位，并且存储在寄生电容中的电荷被放电。 此时，每个存储单元中的开关处于截止状态，因此可以将与模拟信号相对应的电荷保留在存储单元中。

公开(公告)号：US5495296A

公开(公告)日：1996-02-27

申请号：US59561

申请日：1993-05-12

申请人： Shiro Dosho ,  Tatsuro Juri

发明人： Shiro Dosho ,  Tatsuro Juri

IPC分类号： H04N5/14 ,  H03H17/00 ,  H04N7/00 ,  H04N7/46 ,  H04N9/804 ,  H04N9/808 ,  H04N9/87 ,  H04N11/04 ,  H04N11/16 ,  H04N11/22 ,  H04N19/00 ,  H04N19/423 ,  H04N19/426 ,  H04N19/59

CPC分类号： H04N19/59 ,  H04N11/22 ,  H04N9/8042 ,  H04N9/87

摘要： In order to thin an input signal a second multiplexer is switched to output an output of a first adder and a third multiplexer is switched to output an output of a second adder, and a first multiplexer is alternatively switched at every line. A delay circuit memorizes the sum of the two preceding input signals, and the second adder outputs at every other line the sum of image data of a present line and the two preceding lines. To interpolate an input signal, the second multiplexer is switched to output the output of the delay circuit, the first multiplexer is alternatively switched to output either the input signal or the output of the second multiplexer, and the second multiplexer is alternatively switched to output either the output of the first adder or the output of the delay circuit. Thus, the delay circuit outputs at every other line the sum of the two preceding input signals. Because only one delay circuit is needed the size of the perpendicular thinning/interpolation circuit for an image signal is reduced.

摘要翻译： 为了使输入信号变薄，第二多路复用器被切换以输出第一加法器的输出，并且第三多路复用器被切换以输出第二加法器的输出，并且第一多路复用器在每一行交替切换。 延迟电路存储前两个输入信号的和，并且第二加法器在每隔一行输出当前行和前两行的图像数据之和。 为了插入输入信号，第二多路复用器被切换以输出延迟电路的输出，第一多路复用器被交替切换以输出第二多路复用器的输入信号或输出，并且第二多路复用器交替切换以输出 第一加法器的输出或延迟电路的输出。 因此，延迟电路在每隔一行输出前面两个输入信号的和。 因为只需要一个延迟电路，所以减小图像信号的垂直细化/插值电路的尺寸。

公开(公告)号：US08604956B2

公开(公告)日：2013-12-10

申请号：US13073335

申请日：2011-03-28

申请人： Shiro Dosho ,  Kazuo Matsukawa ,  Yosuke Mitani

发明人： Shiro Dosho ,  Kazuo Matsukawa ,  Yosuke Mitani

IPC分类号： H03M3/00

CPC分类号： H03M3/454 ,  H03H11/1252 ,  H03M3/404 ,  H03M3/438

摘要： Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.

公开(公告)号：US08466820B2

公开(公告)日：2013-06-18

申请号：US13025666

申请日：2011-02-11

申请人： Shiro Dosho ,  Kazuo Matsukawa ,  Masao Takayama ,  Yosuke Mitani

发明人： Shiro Dosho ,  Kazuo Matsukawa ,  Masao Takayama ,  Yosuke Mitani

IPC分类号： H03M3/00

CPC分类号： H03M1/12 ,  H03M3/344 ,  H03M3/43 ,  H03M3/454

摘要： An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier.

公开(公告)号：US20060181491A1

公开(公告)日：2006-08-17

申请号：US11401399

申请日：2006-04-11

申请人： Yoshito Date ,  Tetsuro Omori ,  Shiro Dosho ,  Makoto Mizuki

发明人： Yoshito Date ,  Tetsuro Omori ,  Shiro Dosho ,  Makoto Mizuki

IPC分类号： G09G3/30

CPC分类号： G09G3/3283 ,  G09G3/3241 ,  G09G2310/027 ,  G09G2320/0233 ,  G09G2330/028

摘要： The first and second chips are provided side by side. The first chip includes: a current supply section for outputting a drive current, the current supply section including a current mirror; a current distribution MISFET; a current input MISFET for transmitting an electric current to the current supply section, the current input MISFET being connected to the current distribution MISFET; and a second current distribution MISFET. The current distribution MISFET and the second current distribution MISFET constitute a current mirror. The second chip includes a second current input MISFET which is connected to the second current distribution MISFET. The ratio between the W/L ratio of the current distribution MISFET and the W/L ratio of the current input MISFET connected thereto is the same in the first and second chips.

摘要翻译： 第一和第二芯片并排设置。 第一芯片包括：电流供应部分，用于输出驱动电流;电流供应部分包括电流镜; 电流分布MISFET; 电流输入MISFET，用于将电流传输到电流供应部分，电流输入MISFET连接到电流分布MISFET; 和第二电流分布MISFET。 电流分布MISFET和第二电流分布MISFET构成电流镜。 第二芯片包括连接到第二电流分布MISFET的第二电流输入MISFET。 电流分布MISFET的W / L比与与其连接的电流输入MISFET的W / L比之间的比率在第一和第二芯片中是相同的。

公开(公告)号：US06528982B1

公开(公告)日：2003-03-04

申请号：US09697721

申请日：2000-10-27

申请人： Naoshi Yanagisawa ,  Shiro Dosho ,  Kazuhiko Nishikawa ,  Seiji Watanabe ,  Takahiro Bokui

发明人： Naoshi Yanagisawa ,  Shiro Dosho ,  Kazuhiko Nishikawa ,  Seiji Watanabe ,  Takahiro Bokui

IPC分类号： G01R2500

CPC分类号： G01R25/00

摘要： A jitter detector obtains a phase difference between input signals as a digital value to make jitter between the signals easily detectable. The jitter detector includes comparison pulse generator, periodic signal generator, counter and arithmetic unit. The comparison pulse generator outputs one phase difference comparison pulse after another. Each phase difference comparison pulse has a width representing the phase difference between first and second input signals. The periodic signal generator outputs a periodic signal every time a value obtained by accumulating the widths of the phase difference comparison pulses exceeds a predetermined value. Receiving the periodic signal and a clock signal with a period shorter than that of the periodic signal, the counter counts the number of pulses of the clock signal during one period of the periodic signal and outputs a resultant count. And the arithmetic unit detects and outputs a variation in the count as jitter between the first and second input signals.

摘要翻译： 抖动检测器获得输入信号之间的相位差作为数字值，使信号之间的抖动容易检测。 抖动检测器包括比较脉冲发生器，周期信号发生器，计数器和算术单元。 比较脉冲发生器输出一个相差差值比较脉冲。 每个相位差比较脉冲具有表示第一和第二输入信号之间的相位差的宽度。 每当通过累加相位差比较脉冲的宽度获得的值超过预定值时，周期性信号发生器输出周期信号。 接收到周期信号和周期信号的周期信号的时钟信号，计数器在周期信号的一个周期内对时钟信号的脉冲数进行计数，并输出结果计数。 并且算术单元检测并输出计数的变化，作为第一和第二输入信号之间的抖动。