MECHANISMS FOR FORMING IMAGE-SENSOR DEVICE WITH EPITAXIAL ISOLATION FEATURE

    公开(公告)号:US20190244990A1

    公开(公告)日:2019-08-08

    申请号:US16387989

    申请日:2019-04-18

    CPC classification number: H01L27/1464 H01L27/1463 H01L27/14643 H01L27/14689

    Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.

    Structure for stacked logic performance improvement

    公开(公告)号:US10147682B2

    公开(公告)日:2018-12-04

    申请号:US15143950

    申请日:2016-05-02

    Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) having a back-side through-silicon-via (BTSV) with a direct physical connection between a metal interconnect layer and a back-side conductive bond pad. The IC has metal interconnect layers arranged within an inter-level dielectric structure disposed onto a front-side of a substrate. A dielectric layer is arranged along a back-side of the substrate, and a conductive bond pad is arranged over the dielectric layer. A BTSV extends from one of the metal interconnect layers through the substrate and the dielectric layer to the conductive bond pad. A conductive bump is arranged onto the conductive bond pad, which has a substantially planar lower surface extending from over the BTSV to below the conductive bump. Directly connecting the conductive bond pad to the BTSV reduces a size of the conductive bond thereby improving a routing capability of the conductive bond pad.

    Infrared image sensor
    99.
    发明授权

    公开(公告)号:US09929198B2

    公开(公告)日:2018-03-27

    申请号:US14505340

    申请日:2014-10-02

    Abstract: An image sensor includes a substrate, dual-waveband photosensitive devices, at least one infrared photosensitive device, a transparent dielectric layer, at least one infrared band-pass filter, a color filter layer and a micro-lens layer. The dual-waveband photosensitive devices are disposed in the substrate, and each dual-waveband photosensitive device is configured to sense an infrared light and one visible light. The infrared photosensitive device is disposed in the substrate, in which the dual-waveband photosensitive devices and the infrared photosensitive device are arranged in an array. The transparent dielectric layer is disposed over the dual-waveband photosensitive devices and the infrared photosensitive device. The infrared band-pass filter is disposed in the transparent dielectric layer and corresponds to the infrared photosensitive device. The color filter layer is disposed to cover the transparent dielectric layer and the infrared band-pass filter. The micro-lens layer is disposed on the color filter layer.

    Semiconductor device structure with stacked semiconductor dies

    公开(公告)号:US09923011B2

    公开(公告)日:2018-03-20

    申请号:US14993748

    申请日:2016-01-12

    CPC classification number: H01L27/14634 H01L23/481 H01L27/14636 H01L2224/11

    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die and a second semiconductor die. The semiconductor device structure also includes a passivation layer between the first semiconductor die and the second semiconductor die, and the passivation layer is directly bonded to a second interlayer dielectric layer of the second semiconductor die. The semiconductor device structure further includes a conductive feature in via hole and directly bonded to a second conductive line of the second semiconductor die. The semiconductor device structure further includes a second barrier layer between the conductive feature and the passivation layer. The second barrier layer covers sidewalls of the conductive feature and a surface of the conductive feature closer to the first semiconductor die.

Patent Agency Ranking