-
公开(公告)号:US10510592B2
公开(公告)日:2019-12-17
申请号:US15218488
申请日:2016-07-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Min-Feng Kao , Dun-Nian Yaung , Hsing-Chih Lin , Jen-Cheng Liu , Kuan-Chieh Huang
IPC: H01L21/768 , H01L27/088 , H01L23/48 , H01L23/522 , H01L21/762 , H01L21/822 , H01L27/06 , H01L23/525
Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.
-
公开(公告)号:US20190371838A1
公开(公告)日:2019-12-05
申请号:US16113101
申请日:2018-08-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Seiji Takahashi , Chen-Jong Wang , Dun-Nian Yaung , Feng-Chi Hung , Feng-Jia Shiu , Jen-Cheng Liu , Jhy-Jyi Sze , Chun-Wei Chang , Wei-Cheng Hsu , Wei Chuang Wu , Yimin Huang
IPC: H01L27/146
Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.
-
公开(公告)号:US10461109B2
公开(公告)日:2019-10-29
申请号:US15822701
申请日:2017-11-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wei Chuang Wu , Ching-Chun Wang , Dun-Nian Yaung , Feng-Chi Hung , Jen-Cheng Liu , Yen-Ting Chiang , Chun-Yuan Chen , Shen-Hui Hong
IPC: H01L27/146 , H04N5/369 , H04N5/374
Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within a substrate and respectively comprising a photodiode. A boundary deep trench isolation (BDTI) structure is disposed between adjacent pixel regions, extending from a back-side of the substrate to a first depth within the substrate, and surrounding the photodiode. A multiple deep trench isolation (MDTI) structure is disposed within the individual pixel region, extending from the back-side of the substrate to a second depth within the substrate, and overlying the photodiode. A dielectric layer fills in a BDTI trench of the BDTI structure and a MDTI trench of the MDTI structure.
-
公开(公告)号:US20190244990A1
公开(公告)日:2019-08-08
申请号:US16387989
申请日:2019-04-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wen-I Hsu , Feng-Chi Hung , Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu
IPC: H01L27/146
CPC classification number: H01L27/1464 , H01L27/1463 , H01L27/14643 , H01L27/14689
Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.
-
公开(公告)号:US20190115376A1
公开(公告)日:2019-04-18
申请号:US16212784
申请日:2018-12-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Szu-Ying Chen , Min-Feng Kao , Jen-Cheng Liu , Feng-Chi Hung , Dun-Nian Yaung
IPC: H01L27/146
CPC classification number: H01L27/1463 , H01L27/14612 , H01L27/14614 , H01L27/14636 , H01L27/1464 , H01L27/14643 , H01L27/14645 , H01L27/14689
Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device has a gate stack arranged over a first surface of a substrate. A doped isolation feature is arranged within the substrate along opposing sides of the gate stack. A photodetector is also arranged within the substrate. An isolation well region extends below the gate stack and contacts the doped isolation feature along a horizontal plane that is parallel to the first surface and that intersects sides of the photodetector
-
公开(公告)号:US10153316B2
公开(公告)日:2018-12-11
申请号:US15606950
申请日:2017-05-26
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Jeng-Shyan Lin , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung
IPC: H01L27/146 , H01L31/18
Abstract: An image-sensor device is provided. The image-sensor device includes a semiconductor substrate and a radiation-sensing region in the semiconductor substrate. The image-sensor device also includes a doped isolation region adjacent to the radiation-sensing region. The image-sensor device further includes a dielectric film extending into the doped isolation region from a surface of the semiconductor substrate. A portion of the doped isolation region is between the dielectric film and the radiation-sensing region.
-
公开(公告)号:US10147682B2
公开(公告)日:2018-12-04
申请号:US15143950
申请日:2016-05-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Hsun-Ying Huang
IPC: H01L23/48 , H01L23/538 , H01L21/768 , H01L23/31 , H01L23/528 , H01L23/522 , H01L21/683 , H01L23/00 , H01L23/525
Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) having a back-side through-silicon-via (BTSV) with a direct physical connection between a metal interconnect layer and a back-side conductive bond pad. The IC has metal interconnect layers arranged within an inter-level dielectric structure disposed onto a front-side of a substrate. A dielectric layer is arranged along a back-side of the substrate, and a conductive bond pad is arranged over the dielectric layer. A BTSV extends from one of the metal interconnect layers through the substrate and the dielectric layer to the conductive bond pad. A conductive bump is arranged onto the conductive bond pad, which has a substantially planar lower surface extending from over the BTSV to below the conductive bump. Directly connecting the conductive bond pad to the BTSV reduces a size of the conductive bond thereby improving a routing capability of the conductive bond pad.
-
公开(公告)号:US09978805B2
公开(公告)日:2018-05-22
申请号:US15472814
申请日:2017-03-29
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Tzu-Jui Wang , Dun-Nian Yaung , Jen-Cheng Liu , Tzu-Hsuan Hsu , Yuichiro Yamashita
IPC: H01L21/8234 , H01L27/146
CPC classification number: H01L27/14685 , H01L27/14612 , H01L27/14614 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/1464 , H01L27/14643 , H01L27/14689
Abstract: Methods for forming image sensor structures are provided. The method includes forming an isolation structure in a substrate and forming a first light sensing region and a second light sensing region. The method further includes forming a first gate structure and a second gate structure, and the first gate structure and the second gate structure are positioned at a front side of the substrate. The method further includes forming a first source/drain structure adjacent to the first gate structure and a second source/drain structure adjacent to the second gate structure and forming an interlayer dielectric layer over the front side of the substrate. The method further includes forming a contact trench through the interlayer dielectric layer and forming a contact in the contact trench.
-
公开(公告)号:US09929198B2
公开(公告)日:2018-03-27
申请号:US14505340
申请日:2014-10-02
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Keng-Yu Chou , Kazuaki Hashimoto , Jen-Cheng Liu , Jhy-Jyi Sze , Wei-Chieh Chiang , Pao-Tung Chen
IPC: H01L27/146 , H04N5/225 , H04N5/33
CPC classification number: H01L27/14621 , H01L27/1462 , H01L27/14627 , H01L27/14649 , H01L27/14685 , H04N5/2257 , H04N5/332
Abstract: An image sensor includes a substrate, dual-waveband photosensitive devices, at least one infrared photosensitive device, a transparent dielectric layer, at least one infrared band-pass filter, a color filter layer and a micro-lens layer. The dual-waveband photosensitive devices are disposed in the substrate, and each dual-waveband photosensitive device is configured to sense an infrared light and one visible light. The infrared photosensitive device is disposed in the substrate, in which the dual-waveband photosensitive devices and the infrared photosensitive device are arranged in an array. The transparent dielectric layer is disposed over the dual-waveband photosensitive devices and the infrared photosensitive device. The infrared band-pass filter is disposed in the transparent dielectric layer and corresponds to the infrared photosensitive device. The color filter layer is disposed to cover the transparent dielectric layer and the infrared band-pass filter. The micro-lens layer is disposed on the color filter layer.
-
公开(公告)号:US09923011B2
公开(公告)日:2018-03-20
申请号:US14993748
申请日:2016-01-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Hsun-Ying Huang
IPC: H01L27/146 , H01L23/48
CPC classification number: H01L27/14634 , H01L23/481 , H01L27/14636 , H01L2224/11
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die and a second semiconductor die. The semiconductor device structure also includes a passivation layer between the first semiconductor die and the second semiconductor die, and the passivation layer is directly bonded to a second interlayer dielectric layer of the second semiconductor die. The semiconductor device structure further includes a conductive feature in via hole and directly bonded to a second conductive line of the second semiconductor die. The semiconductor device structure further includes a second barrier layer between the conductive feature and the passivation layer. The second barrier layer covers sidewalls of the conductive feature and a surface of the conductive feature closer to the first semiconductor die.
-
-
-
-
-
-
-
-
-