公开(公告)号：US07110282B2

公开(公告)日：2006-09-19

申请号：US10947213

申请日：2004-09-23

申请人： Takashi Kono ,  Takeshi Hamamoto

发明人： Takashi Kono ,  Takeshi Hamamoto

IPC分类号： G11C11/4063 ,  G11C11/4074 ,  G11C7/08 ,  G11C8/08 ,  G11C8/12 ,  G11C8/14 ,  H01L29/772

CPC分类号： G11C8/08 ,  G11C11/401 ,  G11C29/12 ,  G11C2029/1202

摘要： An insulated gate type field effect transistor in a memory cell array is a transistor having a gate insulating film which is thicker than a gate insulating film of an insulated gate type field effect transistor in an array peripheral circuit. DRAM (Dynamic Random Access Memory) cell-based semiconductor memory device can be implemented which allows a burn-in test to be accurately performed without degrading sensing operation characteristics even under a low power supply voltage.

摘要翻译： 存储单元阵列中的绝缘栅型场效应晶体管是具有比阵列外围电路中的绝缘栅型场效应晶体管的栅极绝缘膜厚的栅极绝缘膜的晶体管。 可以实现DRAM（动态随机存取存储器）基于单元的半导体存储器件，其即使在低电源电压下也能够精确地执行老化测试而不降低感测操作特性。

公开(公告)号：US06850406B2

公开(公告)日：2005-02-01

申请号：US10345223

申请日：2003-01-16

申请人： Tadamasa Asami ,  Katsuhiro Yoshida ,  Kunihiko Shimizu ,  Takashi Kono

发明人： Tadamasa Asami ,  Katsuhiro Yoshida ,  Kunihiko Shimizu ,  Takashi Kono

IPC分类号： H01G9/04 ,  C22C32/00 ,  H01G9/00 ,  H01G9/042 ,  H01G9/052 ,  H01G9/055

CPC分类号： H01G9/0032 ,  C22C32/0068 ,  H01G9/0036 ,  H01G9/042 ,  H01G9/0525

摘要： An Nb solid electrolytic capacitor is disclosed which comprises: an anode body made from an Nb-based material, the anode body having a nitrogen content of about 7,500 ppm to about 47,000 ppm; a dielectric layer formed over the surface of the anode body; a solid electrolyte layer formed on the dielectric layer; and a cathode body formed on the surface of the solid electrolyte layer. The Nb solid electrolytic capacitor shows small bias dependence. A method for preparing the same is also disclosed which comprises steps of: forming an anode body from an Nb-based material, the anode body having a nitrogen content of about 7,500 ppm to about 47,000 ppm; forming a dielectric layer over the surface of the anode body; forming a solid electrolyte layer on the dielectric layer; and forming a cathode body on the electrolyte layer.

摘要翻译： 公开了一种Nb固体电解电容器，其包括：由Nb基材料制成的阳极体，所述阳极体的氮含量为约7500ppm至约47,000ppm; 形成在所述阳极体的表面上的电介质层; 形成在电介质层上的固体电解质层; 以及形成在固体电解质层的表面上的阴极体。 Nb固体电解电容器显示出小的偏置依赖性。 还公开了其制备方法，其包括以下步骤：从Nb基材料形成阳极体，所述阳极体的氮含量为约7500ppm至约47,000ppm; 在所述阳极体的表面上形成介电层; 在所述电介质层上形成固体电解质层; 以及在所述电解质层上形成阴极体。

公开(公告)号：US06816422B2

公开(公告)日：2004-11-09

申请号：US10291776

申请日：2002-11-12

申请人： Kei Hamade ,  Takashi Kono ,  Kiyohiro Furutani

发明人： Kei Hamade ,  Takashi Kono ,  Kiyohiro Furutani

IPC分类号： G11C700

CPC分类号： G11C29/40 ,  G11C29/34 ,  G11C2029/0405 ,  G11C2029/2602

摘要： In a multi-bit test, an I/O combiner degenerates data of a plurality of bits read from a memory cell array to first to fourth data bus pairs in parallel and outputs the degenerated data to a fifth data bus. A read amplifier compares a logic level of the degenerated data received from the I/O combiner with a logic level of expected value data. If the logic level of the degenerated data coincides with the logic level of the expected value data, the read amplifier determines that data write and read to and from the plurality of bits have been normally performed. As a result, a semiconductor memory device can detect a word line defect in the multi-bit test.

摘要翻译： 在多位测试中，I / O组合器并行地将从存储单元阵列读取的多个位的数据退格为第一至第四数据总线对，并将退化的数据输出到第五数据总线。 读取放大器将从I / O组合器接收的退化数据的逻辑电平与期望值数据的逻辑电平进行比较。 如果退化数据的逻辑电平与期望值数据的逻辑电平一致，则读取放大器确定对多个位的数据写入和读取已经被正常地执行。 结果，半导体存储器件可以检测多位测试中的字线缺陷。

公开(公告)号：US06496441B2

公开(公告)日：2002-12-17

申请号：US09907743

申请日：2001-07-19

申请人： Takashi Kono ,  Tetsuo Kato

发明人： Takashi Kono ,  Tetsuo Kato

IPC分类号： G11C800

CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C8/12

摘要： By devising the arrangement of memory arrays surrounding the central region of the chip, the total length of a data bus can be reduced. The memory arrays are arranged such that one of two memory arrays that are located at the positions point-symmetric with respect to the central region corresponds to lower DQ terminals, and the other memory array corresponds to upper DQ terminals. Preferably, the memory arrays corresponding to the upper DQ terminals and the memory arrays corresponding to the lower DQ terminals are each located collectively. Thus, a semiconductor memory device with improved data propagation characteristics on the data bus can be provided.

摘要翻译： 通过设计围绕芯片的中心区域的存储器阵列的布置，可以减少数据总线的总长度。 存储器阵列被布置成使得位于相对于中心区域点对称的位置的两个存储器阵列之一对应于较低的DQ端子，而另一个存储器阵列对应于上部DQ端子。 优选地，对应于上部DQ端子的存储器阵列和对应于下部DQ端子的存储器阵列各自集中地定位。 因此，可以提供在数据总线上具有改善的数据传播特性的半导体存储器件。

公开(公告)号：US06262931B1

公开(公告)日：2001-07-17

申请号：US09539893

申请日：2000-03-31

申请人： Takashi Kono ,  Kiyohiro Furutani ,  Takeshi Hamamoto ,  Katsuyoshi Mitsui

发明人： Takashi Kono ,  Kiyohiro Furutani ,  Takeshi Hamamoto ,  Katsuyoshi Mitsui

IPC分类号： G11C800

CPC分类号： G11C8/18 ,  G11C5/147

摘要： A control circuit & mode register outputs a signal responsive to each command to a VDC control circuit. The VDC control circuit outputs a signal PWRUP changing the quantity of a through current Ic of a comparator stored in a VDC in response to the command. The VDC control circuit internally generates a signal of which pulse width corresponds to a prescribed delay time, in response to input of the command. Therefore, activation of each bank may not be monitored but current consumption can be reduced by preferably controlling a power supply current while minimizing the number of delay circuits and wires.

摘要翻译： 控制电路和模式寄存器将响应于每个命令的信号输出到VDC控制电路。 VDC控制电路响应于该命令输出改变存储在VDC中的比较器的直流电流Ic的信号PWRUP。 VDC控制电路根据命令的输入内部产生脉冲宽度对应于规定的延迟时间的信号。 因此，通过优选地控制电源电流同时最小化延迟电路和电线的数量，可以不监视每个组的激活，而可以减少电流消耗。

公开(公告)号：US5847595A

公开(公告)日：1998-12-08

申请号：US757861

申请日：1996-11-27

申请人： Takashi Kono ,  Tsukasa Ooishi ,  Hideto Hidaka

发明人： Takashi Kono ,  Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： G01R31/28 ,  G06F11/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  H03K3/01

CPC分类号： G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/48 ,  G01R31/31721

摘要： A semiconductor memory device includes a mode detection circuit for generating a mode detection signal in response to external input signals /RAS, /CAS and /WE, an internal potential generating circuit for generating and supplying to an output node an internal potential, in response to an activated potential control signal, and an internal potential control circuit for activating a potential control signal when a potential at the output node has not yet reached a predetermined potential in a case where mode detection signal indicates a mode other than the test mode, and for activating the potential control signal when the potential at the output node has not yet reached an externally supplied external reference potential in a case where the mode detection signal indicates the test mode. When external input signals are applied at a predetermined timing, a mode detection signal indicating the test mode is generated, and when the potential at the output node of the internal potential generating circuit has not yet reached the external reference potential, an internal potential is generated and supplied to the output node. Therefore, the internal potential can be controlled in accordance with the external reference potential.

摘要翻译： 半导体存储器件包括：模式检测电路，用于响应于外部输入信号/ RAS，/ CAS和/ WE生成模式检测信号;内部电位产生电路，用于响应于 激活电位控制信号和内部电位控制电路，用于在模式检测信号表示除了测试模式之外的模式的情况下当输出节点的电位尚未达到预定电位时激活电位控制信号，并且 在模式检测信号表示测试模式的情况下，当输出节点的电位尚未达到外部提供的外部参考电位时，激活电位控制信号。 当在预定定时施加外部输入信号时，产生指示测试模式的模式检测信号，并且当内部电位发生电路的输出节点处的电位尚未达到外部参考电位时，产生内部电位 并提供给输出节点。 因此，可以根据外部参考电位来控制内部电位。

公开(公告)号：USD340692S

公开(公告)日：1993-10-26

申请号：US527786

申请日：1990-05-23

申请人： Keiji Iijima ,  Masashi Okazaki ,  Takashi Kono

设计人： Keiji Iijima ,  Masashi Okazaki ,  Takashi Kono

公开(公告)号：US20060280022A1

公开(公告)日：2006-12-14

申请号：US11411938

申请日：2006-04-27

申请人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

发明人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

IPC分类号： G11C8/00

CPC分类号： G11C16/0491 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

摘要： In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.

摘要翻译： 在该AG-AND型闪存中，分层位线配置将存储器阵列分成多个子块，分配新的主位线以便对应于每个子块，并且主位线被选择性地连接 采用通过开关在上层的全局位线，从而在两个主位线之间执行电荷共享写入。 因此，可以以低功耗进行数据写入闪速存储器，并且可以精确地控制阈值电压。

公开(公告)号：US20050168921A1

公开(公告)日：2005-08-04

申请号：US11097316

申请日：2005-04-04

申请人： Mitsunori Sano ,  Takashi Kono

发明人： Mitsunori Sano ,  Takashi Kono

IPC分类号： H01G9/00 ,  H01G9/012 ,  H01G13/00

CPC分类号： H01G9/012 ,  H01G2/02 ,  H01G4/236

摘要： A chip type capacitor is disclosed which has improved bond strength between an anode lead wire and an anode terminal and enhanced reliability. A method for preparing the chip type capacitor and an anode terminal used in the preparation method are also disclosed. The chip type capacitor comprises: a solid electrolytic capacitor element including an element body having an anode body, a dielectric and a cathode body, and an anode lead wire partially extending from the anode body of the element body; and an anode terminal electrically connected to the anode lead wire, the anode lead wire having such a site that about 75% or more of a periphery of a section thereof in the direction substantially perpendicular to the extending direction of the anode lead wire is covered with solidified matter resulting from solidification of a melt, the anode terminal and the anode lead wire being bonded to each other by the solidified matter.

摘要翻译： 公开了一种芯片型电容器，其具有改善的阳极引线和阳极端子之间的结合强度，并提高了可靠性。 还公开了制备方法中制备芯片型电容器和阳极端子的方法。 芯片型电容器包括：固体电解电容器元件，包括具有阳极体，电介质和阴极体的元件体和从元件体的阳极体部分延伸的阳极引线; 以及与阳极引线电连接的阳极端子，具有这样的位置的阳极引线被覆在与阳极引线的延伸方向大致垂直的方向上的部分的周边的大约75％以上的位置 由熔体固化而产生的固化物，阳极端子和阳极引线通过凝固物彼此接合。

公开(公告)号：US06842396B2

公开(公告)日：2005-01-11

申请号：US10387503

申请日：2003-03-14

申请人： Takashi Kono

发明人： Takashi Kono

IPC分类号： G11C11/407 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2227

摘要： A DLL clock control circuit determines whether or not an operating frequency is a low frequency satisfying a prescribed condition, based on signals received from a DLL circuit and a READ control circuit. When the DLL clock control circuit determines that the operating frequency is a low frequency, the DLL clock control circuit outputs a DLL clock received from the DLL circuit if a first signal to be activated in response to a READ command is activated, while when determining that an operating frequency is not a low frequency, outputting a DLL clock received from the DLL circuit if a second signal to be activated in response to an ACT command is activated. As a result, a semiconductor memory device can guarantees a data output operating in data reading and can reduce power consumption during active standby.

摘要翻译： DLL时钟控制电路基于从DLL电路和READ控制电路接收的信号来判定工作频率是否为满足规定条件的低频。 当DLL时钟控制电路确定操作频率是低频时，如果响应于READ命令被激活的第一信号被激活，则DLL时钟控制电路输出从DLL电路接收的DLL时钟，而当确定 如果激活响应于ACT命令被激活的第二信号，则工作频率不是低频，输出从DLL电路接收的DLL时钟。 结果，半导体存储器件可以保证在数据读取中操作的数据输出并且可以在主动待机期间降低功耗。