公开(公告)号：US20110257953A1

公开(公告)日：2011-10-20

申请号：US12762848

申请日：2010-04-19

Applicant: Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

Inventor： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

Abstract translation: 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。 链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

公开(公告)号：US07940814B2

公开(公告)日：2011-05-10

申请号：US12576507

申请日：2009-10-09

Applicant: Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

Inventor： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC: H04J3/04

CPC classification number: H04L5/14 ,  H03K19/17744 ,  H04L27/00

Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

Abstract translation: 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

公开(公告)号：US07834712B2

公开(公告)日：2010-11-16

申请号：US12277810

申请日：2008-11-25

Applicant: Sergey Shumarayev ,  Wilson Wong ,  Allen Chan ,  Ali Atesoglu

Inventor： Sergey Shumarayev ,  Wilson Wong ,  Allen Chan ,  Ali Atesoglu

IPC: H03B5/00

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/011

Abstract: An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.

Abstract translation: 振荡器电路包括通过第一导电层中的路由导体交叉耦合的晶体管。 振荡器电路还包括第二导电层中的变容二极管，电容器和选项导体。 选项导体形成晶体管之一和电容器或变容二极管之间的连接的至少一部分。

公开(公告)号：US07693691B1

公开(公告)日：2010-04-06

申请号：US11524012

申请日：2006-09-19

Applicant: Yuming Tao ,  William W. Bereza ,  Rakesh H. Patel ,  Tad Kwasniewski ,  Sergey Shumarayev ,  Shoujun Wang ,  Miao Li

Inventor： Yuming Tao ,  William W. Bereza ,  Rakesh H. Patel ,  Tad Kwasniewski ,  Sergey Shumarayev ,  Shoujun Wang ,  Miao Li

IPC: G06F17/50 ,  H04B1/04

CPC classification number: G06F17/5009

Abstract: Systems and methods for accurately and quickly simulating link performance of a transceiver operating with any given transmission medium are provided. Accurate and quick link simulations may be provided using a link simulation platform. The link simulation platform may simulate link performance using transceiver behavioral models (e.g., transmitter and receiver behavioral models) that incorporate silicon level parameters, which parameters enable the behavioral models to substantially emulate the actual behavior of the transceiver portions of the link.

Abstract translation: 提供了用于准确和快速地模拟使用任何给定传输介质工作的收发器的链路性能的系统和方法。 可以使用链路仿真平台提供准确和快速的链路模拟。 链路仿真平台可以使用包含硅级参数的收发机行为模型（例如，发射机和接收机行为模型）来模拟链路性能，这些参数使得行为模型能够基本上模拟链路的收发器部分的实际行为。

公开(公告)号：US07638990B1

公开(公告)日：2009-12-29

申请号：US11754295

申请日：2007-05-27

Applicant: Sergey Shumarayev ,  Simardeep Maangat

Inventor： Sergey Shumarayev ,  Simardeep Maangat

IPC: G05F1/40 ,  G05F1/56

CPC classification number: G05F1/56

Abstract: A power management system on an integrated circuit can include a first switch and a second switch. A regulator circuit provides current from a first supply voltage to a circuit block when the first switch is closed. The second switch provides current from a second supply voltage to the circuit block when the second switch is closed.

Abstract translation: 集成电路上的电源管理系统可以包括第一开关和第二开关。 当第一开关闭合时，调节器电路将电流从第一电源电压提供给电路块。 当第二开关闭合时，第二开关将电流从第二电源电压提供给电路块。

公开(公告)号：US07589651B1

公开(公告)日：2009-09-15

申请号：US11467332

申请日：2006-08-25

Applicant: Sergey Shumarayev ,  Rakesh H. Patel ,  Wilson Wong

Inventor： Sergey Shumarayev ,  Rakesh H. Patel ,  Wilson Wong

IPC: H03M1/00

CPC classification number: H03K19/17744 ,  H03K19/17732

Abstract: A serial interface for a programmable logic device (PLD) uses an analog-to-digital converter (ADC) in place of conventional signal detect and receiver detect circuitry. A separate ADC can be used in each receiver and each transmitter in each serial interface on the PLD. Alternatively, time division multiplexing can be used to allow the receiver and transmitter in each receiver/transmitter pair, or even multiple receiver/transmitter pairs, to share a single ADC. When none of the receiver/transmitter pairs associated with a particular ADC is being used, the ADC can be accessed for use simply as an ADC.

Abstract translation: 用于可编程逻辑器件（PLD）的串行接口使用模数转换器（ADC）来代替传统的信号检测和接收器检测电路。 在PLD的每个串行接口中的每个接收器和每个发射器中可以使用单独的ADC。 或者，可以使用时分复用来允许每个接收机/发射机对中的接收机和发射机，或甚至多个接收机/发射机对共享单个ADC。 当没有使用与特定ADC相关联的接收器/发送器对时，ADC可以被简单地用作ADC。

公开(公告)号：US07411464B1

公开(公告)日：2008-08-12

申请号：US11430469

申请日：2006-05-08

Applicant: Tim T Hoang ,  Sergey Shumarayev

Inventor： Tim T Hoang ,  Sergey Shumarayev

IPC: H03B5/24 ,  H03L1/00 ,  H03L7/099

CPC classification number: H03K5/1565 ,  H03K3/0315 ,  H03L7/18

Abstract: An oscillator circuit can generate a periodic signal, and a frequency adjustment circuit can adjust the frequency of the periodic signal. The periodic signal may include phase jitter. In one aspect of the invention, the phase jitter may be mitigated by connecting other circuitry to the oscillator circuit and allowing the other circuitry to draw current. In one embodiment, the other circuitry is connected in parallel with the oscillator circuit. In one embodiment, the other circuitry is configured to draw greater current to mitigate more phase jitter and to draw less current to mitigate less phase jitter. In one embodiment, a greater portion of the other circuitry is connected to the oscillator circuit for higher frequencies and a lesser portion of the other circuitry is connected to the oscillator circuit for lower frequencies.

Abstract translation: 振荡器电路可以产生周期信号，并且频率调节电路可以调节周期信号的频率。 周期信号可能包括相位抖动。 在本发明的一个方面，通过将其它电路连接到振荡器电路并允许其它电路抽取电流可以减轻相位抖动。 在一个实施例中，另一个电路与振荡器电路并联连接。 在一个实施例中，另一个电路被配置为绘制更大的电流以减轻更多的相位抖动并绘制更少的电流以减轻较少的相位抖动。 在一个实施例中，其他电路的较大部分连接到振荡器电路用于较高频率，而另一电路的较小部分连接到用于较低频率的振荡器电路。

公开(公告)号：US07355462B1

公开(公告)日：2008-04-08

申请号：US11456484

申请日：2006-07-10

Applicant: Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev

Inventor： Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev

IPC: H03L7/06

CPC classification number: H03L7/089 ,  H03L7/093 ,  H03L7/18

Abstract: A digital controller for a voltage controlled oscillator (VCO) is provided within a phase lock loop (PLL). The digital controller includes a digital filter having first and second inputs for receiving upward and downward adjustment signals, respectively. The digital filter generates an increment signal and a decrement signal in response to the upward and downward adjustment signals, respectively. The digital controller includes a digital counter having first and second inputs for receiving the increment and decrement signals, respectively. The digital counter generates a multi-bit output signal that represents a running sum of the increment and decrement signals. The digital controller further includes a digital-to-analog converter (DAC) having an input for receiving the running sum output signal generated by the digital counter. The DAC is defined to generate a control voltage for the VCO in response to receipt of the running sum output signal from the digital counter.

Abstract translation: 在锁相环（PLL）内提供压控振荡器（VCO）的数字控制器。 数字控制器包括具有分别用于接收上下调节信号的第一和第二输入的数字滤波器。 数字滤波器分别响应于上下调节信号产生增量信号和减量信号。 数字控制器包括一个数字计数器，它具有分别用于接收增量和减量信号的第一和第二输入端。 数字计数器产生一个多位输出信号，表示增量和减量信号的运行和。 数字控制器还包括具有用于接收由数字计数器产生的运行和输出信号的输入的数模转换器（DAC）。 DAC被定义为响应于来自数字计数器的运行和输出信号的接收而产生用于VCO的控制电压。

公开(公告)号：US20070127616A1

公开(公告)日：2007-06-07

申请号：US11292565

申请日：2005-12-02

Applicant: Sergey Shumarayev ,  Rakesh Patel

Inventor： Sergey Shumarayev ,  Rakesh Patel

IPC: H03D3/24

CPC classification number: H03K19/17744 ,  H03L7/0995

Abstract: A field-programmable gate array (“FPGA”) may include data receiver and/or transmitter circuitry that is adapted to receive and/or transmit data at any frequency(ies) or data rate(s) in a wide range of possible frequencies or data rates. Phase-locked loop (PLL) circuitry may be needed for operation of such receiver and/or transmitter circuitry. For satisfactory operation over the wide frequency range, multiple PLL circuits are provided. One of these PLL circuits may be capable of operating over the entire frequency range, possibly with better jitter performance in some portions of the range than in other portions of the range. One or more other PLL circuits may be provided that are focused on particular parts of the broad range, especially where the jitter performance of the first-mentioned PLL may not be adequate to meet some possible needs.

Abstract translation: 现场可编程门阵列（“FPGA”）可以包括数据接收器和/或发射机电路，其适于在宽范围的可能频率中以任何频率或数据速率接收和/或发射数据，或 数据速率。 可能需要锁相环（PLL）电路来操作这种接收器和/或发射器电路。 为了在宽频率范围内的令人满意的操作，提供了多个PLL电路。 这些PLL电路中的一个可能能够在整个频率范围内运行，可能在该范围的某些部分中具有比该范围的其他部分更好的抖动性能。 可以提供一个或多个其他PLL电路，其集中在宽范围的特定部分上，特别是在首先提到的PLL的抖动性能可能不足以满足一些可能需要的地方。

公开(公告)号：US20070030184A1

公开(公告)日：2007-02-08

申请号：US11364589

申请日：2006-02-27

Applicant: Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

Inventor： Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

IPC: H03M9/00

CPC classification number: H03K19/00 ,  H03K19/17744 ,  H03M9/00 ,  H04L1/243 ,  H04L7/0008 ,  H04L7/033 ,  H04L25/0266

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract translation: 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。