公开(公告)号：US20050105326A1

公开(公告)日：2005-05-19

申请号：US11009449

申请日：2004-12-13

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C11/15 ,  G11C5/00 ,  G11C7/00 ,  G11C11/00 ,  G11C11/16 ,  G11C11/34 ,  H01L27/22 ,  H01L31/0328

CPC分类号： G11C29/787 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693

摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

摘要翻译： 虚拟单元包括：多个第一存储单元MC，用于存储多个字线WR0至WR7与多个第一数据线D 0至D 7之间的交点处的“1”或“0” 多个用于存储“1”或“0”的第一虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” “，布置在字线WR0至WR7之间的交点处和第二伪数据线DD 1之间。

公开(公告)号：US06680867B2

公开(公告)日：2004-01-20

申请号：US10357222

申请日：2003-02-04

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C700

CPC分类号： G11C29/787 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693

摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

摘要翻译： 虚拟单元包括多个用于存储“1”或“0”的第一存储单元MC，其布置在多个字线WR0至WR7与多个第一数据线D0至D7之间的交点处，多个第一 用于存储“1”或“0”的虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” 字线WR0〜WR7与第二伪数据线DD1的交点。

公开(公告)号：US06677633B2

公开(公告)日：2004-01-13

申请号：US10408221

申请日：2003-04-08

申请人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka

发明人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka

IPC分类号： H01L2978

CPC分类号： H01L27/108 ,  H01L27/10823

摘要： In manufacturing a semiconductor memory by using conventional gain cells, it is difficult to integrate them similarly to 1T1C cells of a DRAM if mask alignment accuracy is considered. In order to achieve integration similarly to that of 1T1C cells by using gain cells, a memory cell block constituted as follows is used. A memory block (MCT) comprises a plurality of memory cells (MC0-MC3). Each memory cell includes a PMOS transistor (M0) for writing and an NMOS transistor (M1) for reading, and information is stored by holding electric charge in a storage node. The write transistors (M0) are arranged in parallel in a plurality of cells, each source-drain path is connected to a data line (DL). The read transistors (M1) are connected in series in a plurality of cells, and are connected to the data line (DL) via a block selection transistor (MB).

摘要翻译： 在通过使用常规增益单元制造半导体存储器时，如果考虑到掩模对准精度，则难以将其类似于DRAM的1T1C单元进行集成。 为了通过使用增益单元来实现与1T1C单元的集成相似的集成，使用如下构成的存储单元块。 存储块（MCT）包括多个存储单元（MC0-MC3）。 每个存储单元包括用于写入的PMOS晶体管（M0）和用于读取的NMOS晶体管（M1），并且通过在存储节点中保持电荷来存储信息。 写入晶体管（M0）在多个单元中并联布置，每个源极 - 漏极路径连接到数据线（DL）。 读取晶体管（M1）串联连接在多个单元中，并通过块选择晶体管（MB）连接到数据线（DL）。

公开(公告)号：US06570206B1

公开(公告)日：2003-05-27

申请号：US10239417

申请日：2002-09-24

申请人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka

发明人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka

IPC分类号： H01L2978

CPC分类号： G11C11/405 ,  G11C11/4097 ,  H01L27/108 ,  H01L27/10873

摘要： In manufacturing a semiconductor memory by using conventional gain cells, it is difficult to integrate them similarly to 1T1C cells of a DRAM if mask alignment accuracy is considered. In order to achieve integration similarly to that of 1T1C cells by using gain cells, a memory cell block constituted as follows is used. A memory block (MCT) comprises a plurality of memory cells (MC0-MC3). Each memory cell includes a PMOS transistor (M0) for writing and an NMOS transistor (M1) for reading, and information is stored by holding electric charge in a storage node. The write transistors (M0) are arranged in parallel in a plurality of cells, each source-drain path is connected to a data line (DL). The read transistors (M1) are connected in series in a plurality of cells, and are connected to the data line (DL) via a block selection transistor (MB).

摘要翻译： 在通过使用常规增益单元制造半导体存储器时，如果考虑到掩模对准精度，则难以将其类似于DRAM的1T1C单元进行集成。 为了通过使用增益单元来实现与1T1C单元的集成相似的集成，使用如下构成的存储单元块。 存储块（MCT）包括多个存储单元（MC0-MC3）。 每个存储单元包括用于写入的PMOS晶体管（M0）和用于读取的NMOS晶体管（M1），并且通过在存储节点中保持电荷来存储信息。 写入晶体管（M0）在多个单元中并联布置，每个源极 - 漏极路径连接到数据线（DL）。 读取晶体管（M1）串联连接在多个单元中，并通过块选择晶体管（MB）连接到数据线（DL）。

公开(公告)号：US06452858B1

公开(公告)日：2002-09-17

申请号：US09706374

申请日：2000-11-03

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C11407

CPC分类号： G11C8/08 ,  G11C11/4074 ,  G11C11/4085

摘要： A semiconductor device to output voltages at three levels to a word driver while alleviating the breakdown voltage in the MOS transistor. This invention is comprised of a breakdown-voltage reducing MOS transistor inserted in the word driver and two NMOS transistors to supply a read-out voltage to a word line. The word driver is moreover controlled by different voltage amplitudes on the main word lines and the common word lines.

摘要翻译： 一种半导体器件，用于将三电平的电压输出到字驱动器，同时减轻MOS晶体管中的击穿电压。 本发明包括插入字驱动器中的击穿电压降低MOS晶体管和两个NMOS晶体管，以将读出电压提供给字线。 此外，字驱动器通过主字线和公用字线上的不同电压幅度进行控制。

公开(公告)号：US08773919B2

公开(公告)日：2014-07-08

申请号：US13300139

申请日：2011-11-18

申请人： Seiji Miura ,  Satoru Hanzawa

发明人： Seiji Miura ,  Satoru Hanzawa

IPC分类号： G11C7/00 ,  G11C13/00 ,  G11C8/08 ,  G11C8/18

CPC分类号： G11C13/0007 ,  G11C8/08 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0088 ,  G11C2211/5623

摘要： In a phase change memory, when M bit (8 bits=1 byte) data is written, erase operation and program operation are performed in units of n bit (M>n) data. Further, when M bit data is written, program operation is performed in units of the n bit (M>n) data. Further, when M bit data is read from the memory cell, read operation is performed in units of the n bit (M>n) data. For example, when the data is written into to the phase change memory, the data is not overwritten but program is performed after once erasing the target memory cell. The data size for erasure and the data size for program are made equal. Erase and program operation are performed only for the demanded data size.

摘要翻译： 在相变存储器中，当写入M位（8位= 1字节）数据时，以n位（M> n）数据为单位执行擦除操作和编程操作。 此外，当写入M位数据时，以n位（M> n）数据为单位执行编程操作。 此外，当从存储单元读取M位数据时，以n位（M> n）数据为单位执行读操作。 例如，当数据被写入相变存储器时，数据不被重写，而是在擦除目标存储单元之后执行程序。 擦除的数据大小和程序的数据大小相等。 擦除和编程操作仅针对所需的数据大小执行。

公开(公告)号：US08711637B2

公开(公告)日：2014-04-29

申请号：US13300139

申请日：2011-11-18

申请人： Seiji Miura ,  Satoru Hanzawa

发明人： Seiji Miura ,  Satoru Hanzawa

IPC分类号： G11C7/00

摘要： In a phase change memory, when M bit (8 bits=1 byte) data is written, erase operation and program operation are performed in units of n bit (M>n) data. Further, when M bit data is written, program operation is performed in units of the n bit (M>n) data. Further, when M bit data is read from the memory cell, read operation is performed in units of the n bit (M>n) data. For example, when the data is written into to the phase change memory, the data is not overwritten but program is performed after once erasing the target memory cell. The data size for erasure and the data size for program are made equal. Erase and program operation are performed only for the demanded data size.

公开(公告)号：US08634257B2

公开(公告)日：2014-01-21

申请号：US13466866

申请日：2012-05-08

申请人： Satoru Hanzawa ,  Hiroyuki Minemura

发明人： Satoru Hanzawa ,  Hiroyuki Minemura

IPC分类号： G11C7/22

CPC分类号： H01L27/2454 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/18 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144

摘要： A semiconductor storage device crystallizes variable resistive element material layers arranged on side surfaces of multiple semiconductor layers in a stacked structure concurrently by applying a first current to any one of semiconductor layers in the stacked structure, and thereafter applies a second current to semiconductor layers other than a semiconductor layer to which the first current was applied.

摘要翻译： 半导体存储装置通过向堆叠结构中的任一个半导体层施加第一电流，同时以层叠结构使配置在多个半导体层的侧面上的可变电阻元件材料层结晶化，然后向第二电流施加除了 施加了第一电流的半导体层。

公开(公告)号：US20120211718A1

公开(公告)日：2012-08-23

申请号：US13440225

申请日：2012-04-05

申请人： AKIO SHIMA ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

发明人： AKIO SHIMA ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

IPC分类号： H01L45/00

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1683

摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

摘要翻译： 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以配置三维存储器 单元格阵列。 存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。 通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

公开(公告)号：US08179739B2

公开(公告)日：2012-05-15

申请号：US12672685

申请日：2007-08-10

申请人： Satoru Hanzawa ,  Fumihiko Nitta ,  Nozomu Matsuzaki ,  Toshihiro Tanaka

发明人： Satoru Hanzawa ,  Fumihiko Nitta ,  Nozomu Matsuzaki ,  Toshihiro Tanaka

IPC分类号： G11C8/00

CPC分类号： G11C5/06 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144

摘要： A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a select transistor (CT). A buffer cell is arranged between a sense amplifier (SA) and a memory cell array (MCA) and between a word driver (WDB) and the memory cell array. The buffer cell is formed of the resistive storage element (RE) and the select transistor (CT) same as those of the memory cell. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

摘要翻译： 一种能够制造半导体器件的技术，而不会在涉及包括由可变电阻器和选择晶体管（CT）使用存储元件（RE）的存储器单元形成的存储单元阵列的相变存储器的制造设备中产生污染。 缓冲单元布置在读出放大器（SA）和存储单元阵列（MCA）之间以及字驱动器（WDB）和存储单元阵列之间。 缓冲单元由与存储单元相同的电阻存储元件（RE）和选择晶体管（CT）形成。 存储单元中的电阻存储元件通过形成在电阻存储元件上方的触点连接到位线。 同时，在缓冲单元中，电阻性存储元件之上不形成接触，并且在处理存储单元中的接触时保持被绝缘体覆盖的状态。 通过这种处理方法，可以避免在电阻存储元件中使用的硫族化物膜的曝光和升华。