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196 条记录 (耗时 0.035 秒)

    Phase change material memory device
    91.
    发明授权
    Phase change material memory device 有权
    相变材料存储器件

    公开(公告)号：US06908812B2

    公开(公告)日：2005-06-21

    申请号：US10426380

    申请日：2003-04-30

    申请人： Tyler A. Lowrey

    发明人： Tyler A. Lowrey

    IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L21/00

    CPC分类号： H01L45/06 ,  H01L27/2463 ,  H01L45/124 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1691

    摘要： A phase change material memory cell may be formed with singulated, cup-shaped phase change material. The interior of the cup-shaped phase change material may be filled with a thermal insulating material. As a result, heat losses upwardly through the phase change material may be reduced and adhesion problems between the phase change material and the rest of the device may likewise be reduced in some embodiments. In addition, a barrier layer may be provided between the upper electrode and the remainder of the device that may reduce species incorporation from the top electrode into the phase change material, in some embodiments. Chemical mechanical planarization may be utilized to define the phase change material reducing the effects of phase change material dry etching in some embodiments.

    摘要翻译： 相变材料存储单元可以形成为单切形的杯形相变材料。 杯状相变材料的内部可以填充绝热材料。 结果，在一些实施例中，相变材料向上的热损失可能会降低，同相材料与器件的其余部分之间的粘合问题同样可以减少。 此外，在一些实施例中，可以在上电极和器件的其余部分之间提供阻挡层，其可以减少从顶电极引入到相变材料中的物质。 在一些实施方案中，化学机械平面化可用于限定相变材料减少相变材料干蚀刻的影响。

    Methods of fabricating buried digit lines
    92.
    发明授权
    Methods of fabricating buried digit lines 有权
    埋地数字线的制作方法

    公开(公告)号：US06825109B2

    公开(公告)日：2004-11-30

    申请号：US10425130

    申请日：2003-04-28

    申请人： Tyler A. Lowrey

    发明人： Tyler A. Lowrey

    IPC分类号： H01L214763

    CPC分类号： H01L21/76897 ,  H01L21/76838 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10811 ,  H01L27/10885 ,  H01L27/10888

    摘要： A method for electrically linking the contacts of a semiconductor device to their corresponding digit lines includes disposing a quantity of mask material into a trench through which the contact is exposed. The mask also abuts a connect region of a conductive element of a corresponding conductive line and, therefore, protrudes somewhat over a surface of the semiconductor device. A layer of insulative material is formed over the semiconductor device with the mask exposed therethrough. The mask is then removed, leaving open cavities, including the trench and a strap region continuous with both the trench and a connect region of the corresponding conductive line. Conductive material is introduced into each open cavity to define conductive plugs or studs and conductive straps that are electrically isolated from one another. Semiconductor devices including features that have been fabricated in accordance with the method are also within the scope of the present invention.

    摘要翻译： 将半导体器件的触点与其对应的数字线电连接的方法包括将一定数量的掩模材料设置在暴露触点的沟槽中。 掩模还邻接相应导电线的导电元件的连接区域，因此在半导体器件的表面上稍微突出。 在半导体器件上形成绝缘材料层，其中掩模暴露在其中。 然后去除掩模，留下开放的空腔，包括沟槽和与沟槽和相应导电线的连接区域连续的带区域。 将导电材料引入每个开放的空腔中以限定彼此电隔离的导电塞或螺栓和导电带。 包括根据该方法制造的特征的半导体器件也在本发明的范围内。

    Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer
    94.
    发明授权
    Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer 失效
    具有硅化钛界面的硅的低电阻接触和无定形氮化钛氮化硼阻挡层

    公开(公告)号：US06624517B1

    公开(公告)日：2003-09-23

    申请号：US09505213

    申请日：2000-02-16

    申请人： Gurtej S. Sandhu ,  Trung T. Doan ,  Tyler A. Lowrey

    发明人： Gurtej S. Sandhu ,  Trung T. Doan ,  Tyler A. Lowrey

    IPC分类号： H01L2348

    CPC分类号： H01L21/76855 ,  C23C16/34 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862

    摘要： This invention constitutes a contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon, or of metal, such as tungsten, follows, and proceeds until the contact opening is completely filled with either polycrystalline silicon or metal.

    摘要翻译： 本发明构成了采用利用四 - 二烷基酰胺基钛，Ti（NMe 2）4作为前体的低压化学气相沉积（LPCVD）形成的非晶氮化钛阻挡层的接触结构。 通过将通过电介质层的接触开口蚀刻到要进行电接触的扩散区域来制造接触结构。 钛金属沉积在晶片的表面上，使得扩散区域的暴露表面完全被金属层覆盖。 钛金属层的至少一部分最终被转化为硅化钛，从而在扩散区的表面提供优异的导电界面。 然后使用LPCVD工艺沉积氮化钛阻挡层，涂覆接触开口的壁和底板。 多晶硅或金属如钨的化学气相沉积随后进行，直到接触开口完全充满多晶硅或金属。

    Method of making memory cell arrays
    95.
    发明授权
    Method of making memory cell arrays 有权
    制造存储单元阵列的方法

    公开(公告)号：US06607944B1

    公开(公告)日：2003-08-19

    申请号：US09918345

    申请日：2001-07-30

    申请人： Luan Tran ,  D. Mark Duncan ,  Tyler A. Lowrey ,  Rob B. Kerr ,  Kris K. Brown

    发明人： Luan Tran ,  D. Mark Duncan ,  Tyler A. Lowrey ,  Rob B. Kerr ,  Kris K. Brown

    IPC分类号： H01L2182

    CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L27/10885

    摘要： A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.

    摘要翻译： 存储器件包括存储器单元，位线，通常与位线平行地运行的有源区线以及在每个有源区域线中形成的晶体管，并将存储单元电耦合到相应的位线。 每个位线包括以一角度与有源区域线的相应部分相交的倾斜部分。 将位线电耦合到有源区域线的部分的触点形成在通常由位线到有源区域线的成角度的交叉点限定的区域中。 存储器单元可以具有约6F2的面积，并且位线可以以折叠位线配置耦合到读出放大器。 每个位线包括第一电平部分和第二电平部分。

    Method for reading a structural phase-change memory
    96.
    发明授权
    Method for reading a structural phase-change memory 有权
    读取结构相变存储器的方法

    公开(公告)号：US06590807B2

    公开(公告)日：2003-07-08

    申请号：US09921853

    申请日：2001-08-02

    申请人： Tyler A. Lowrey

    发明人： Tyler A. Lowrey

    IPC分类号： G11C1136

    CPC分类号： G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0092

    摘要： A cell in a structural phase-change memory is programmed by raising cell voltage and cell current to programming threshold levels, and then lowering these to quiescent levels below their programming levels. A precharge pulse is then applied which raises the bitline voltage of the selected cell and does not raise the cell voltage and cell current to their programming levels. Then, the cell current is raised to a read level which is below the programming threshold level, and the bitline voltage is compared to a reference voltage while the cell current is at the read level.

    摘要翻译： 结构相变存储器中的单元通过将单元电压和单元电流提高到编程阈值电平来编程，然后将其降低到低于其编程电平的静态电平。 然后施加预充电脉冲，其提高所选择的单元的位线电压，并且不将单元电压和单元电流提高到其编程电平。 然后，电池电流升高到低于编程阈值电平的读取电平，并且在电池电流处于读取电平的同时将位线电压与参考电压进行比较。

    Utilizing atomic layer deposition for programmable device
    97.
    发明授权
    Utilizing atomic layer deposition for programmable device 有权
    利用原子层沉积可编程器件

    公开(公告)号：US06511867B2

    公开(公告)日：2003-01-28

    申请号：US09896529

    申请日：2001-06-30

    申请人： Tyler A. Lowrey ,  Charles H. Dennison

    发明人： Tyler A. Lowrey ,  Charles H. Dennison

    IPC分类号： H01L2182

    CPC分类号： H01L21/7685 ,  H01L21/28562 ,  H01L21/76888 ,  H01L27/24

    摘要： In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the dielectric, utilizing atomic layer deposition (ALD). A programmable material is formed on the electrode and a conductor is formed to the programmable material. In an aspect, a barrier is conformally deposited utilizing ALD, between the electrode and the programmable material.

    摘要翻译： 在一方面，提供一种设置和重新编程可编程设备的状态的设备。 在一方面，提供了一种方法，使得通过暴露接触的电介质形成开口，接触形成在基底上。 利用原子层沉积（ALD）将电极保形地沉积在电介质的壁上。 可编程材料形成在电极上，导体形成可编程材料。 在一个方面，在电极和可编程材料之间利用ALD共形沉积屏障。

    Method for fabricating a floating gate semiconductor device
    99.
    发明授权
    Method for fabricating a floating gate semiconductor device 有权
    浮栅半导体器件的制造方法

    公开(公告)号：US06420249B1

    公开(公告)日：2002-07-16

    申请号：US09536931

    申请日：2000-03-27

    申请人： Trung Tri Doan ,  Tyler A. Lowrey

    发明人： Trung Tri Doan ,  Tyler A. Lowrey

    IPC分类号： H01L218247

    CPC分类号： H01L29/66825 ,  H01L21/28273

    摘要： A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.

    摘要翻译： 提供了一种用于形成诸如电可擦除可编程只读存储器的浮置栅极半导体器件的方法。 该器件包括具有电隔离的有源区的硅衬底。 栅极氧化物以及FET的其它部件（例如，源极，漏极）形成在有源区域中。 通过将导电层（例如多晶硅）沉积到栅极氧化物上而形成自对准浮栅。 然后将导电层化学机械平面化到隔离层的端点，使得去除凹部中和栅极氧化物上的材料以外的所有导电层。 在形成浮栅之后，在浮栅上形成绝缘层，在绝缘层上形成控制栅。