公开(公告)号：US06200907B1

公开(公告)日：2001-03-13

申请号：US09204216

申请日：1998-12-02

申请人： Fei Wang ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Scott A. Bell ,  Harry J. Levinson ,  Chih Yuh Yang

发明人： Fei Wang ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Scott A. Bell ,  Harry J. Levinson ,  Chih Yuh Yang

IPC分类号： H01L21302

CPC分类号： H01L21/32139 ,  H01L21/0275 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76838

摘要： In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a barrier metal layer over the oxide layer; depositing an ultra-thin photoresist over the barrier metal layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the barrier metal layer; etching the exposed portion of the barrier metal layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.

摘要翻译： 在一个实施例中，本发明涉及一种形成金属线的方法，包括以下步骤：提供包括金属层的半导体衬底，金属层上的氧化物层和氧化物层上的阻挡金属层; 在阻挡金属层上沉积超薄光致抗蚀剂，超薄光致抗蚀剂具有小于约的厚度; 用波长约250nm或更小的电磁辐射照射超薄光致抗蚀剂; 显影暴露一部分阻挡金属层的超薄光刻胶; 蚀刻暴露部分氧化物层的阻挡金属层的暴露部分; 蚀刻暴露出金属层的一部分的氧化物层的暴露部分; 并且蚀刻金属层的暴露部分从而形成金属线。

公开(公告)号：US06184128B2

公开(公告)日：2001-02-06

申请号：US09497222

申请日：2000-01-31

申请人： Fei Wang ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Scott A. Bell ,  Harry J. Levinson ,  Chih Yuh Yang

发明人： Fei Wang ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Scott A. Bell ,  Harry J. Levinson ,  Chih Yuh Yang

IPC分类号： H01L214763

CPC分类号： H01L21/7681 ,  H01L21/31144

摘要： In one embodiment, the present invention relates to a dual damascene method involving the steps of providing a substrate having a first low k material layer; forming a first hard mask layer over the first low k material layer; patterning a first opening having a first width in the first hard mask layer using a first photoresist thereby exposing a portion of the first low k material layer; removing the first photoresist; depositing a second low k material layer over the patterned first hard mask layer and the exposed portion of the first low k material layer; forming a second hard mask layer over the second low k material layer; patterning a second opening having a width larger than the first width in the second hard mask layer using a second photoresist thereby exposing a portion of the second low k material layer; anisotropically etching the exposed portions of the first and second low k material layers; and removing the second photoresist, wherein and at least one of the first photoresist and the second photoresist have a thickness of about 1,500 Å or less.

摘要翻译： 在一个实施例中，本发明涉及一种双镶嵌方法，包括以下步骤：提供具有第一低k材料层的基底; 在所述第一低k材料层上形成第一硬掩模层; 使用第一光致抗蚀剂构图在第一硬掩模层中具有第一宽度的第一开口，从而暴露第一低k材料层的一部分; 去除第一光致抗蚀剂; 在图案化的第一硬掩模层和第一低k材料层的暴露部分上沉积第二低k材料层; 在所述第二低k材料层上形成第二硬掩模层; 使用第二光致抗蚀剂构图在第二硬掩模层中形成具有大于第一宽度的宽度的第二开口，从而暴露第二低k材料层的一部分; 各向异性地蚀刻第一和第二低k材料层的暴露部分; 并且去除所述第二光致抗蚀剂，其中所述第一光致抗蚀剂和所述第二光致抗蚀剂中的至少一个具有大约等于或小于1500埃的厚度。

公开(公告)号：US6121663A

公开(公告)日：2000-09-19

申请号：US992952

申请日：1997-12-18

申请人： William G. En ,  Darin A. Chan ,  David K. Foote ,  Fei Wang ,  Minh Van Ngo

发明人： William G. En ,  Darin A. Chan ,  David K. Foote ,  Fei Wang ,  Minh Van Ngo

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L21/76895 ,  H01L21/76897

摘要： At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.

摘要翻译： 在晶体管布置内提供至少一个图形化的介电层，以防止局部互连在形成局部互连所用的蚀刻开口的镶嵌层形成期间由于不对准而电接触栅极导体。 通过在局部互连蚀刻工艺期间通过选择性蚀刻穿过多个电介质层，将图案化的介电层留在原位以防止栅极短路到相邻的局部互连，其稍微错位。

公开(公告)号：US6025462A

公开(公告)日：2000-02-15

申请号：US33882

申请日：1998-03-03

申请人： Fei Wang ,  R. David Rauh

发明人： Fei Wang ,  R. David Rauh

IPC分类号： C08G61/02 ,  C08G61/12 ,  C08G83/00 ,  C08L65/00 ,  C08L65/02 ,  H01L51/00 ,  H01L51/30 ,  H01L51/50 ,  C08G15/00

CPC分类号： C08L65/02 ,  C08G61/02 ,  C08G61/126 ,  C08G83/002 ,  C08G83/005 ,  C08L65/00 ,  H01L51/0095 ,  C08G2261/312 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/5012

摘要： Conductive polymers having a star structure comprising a central core with multiple attachment sites and conjugated charge transporting arms radiating therefrom. The cores are derived from hyperbranched polymers, dendrimers, or other molecules with a multiplicity of attachment sites. The arms are derived from conjugated oligomers and polymers such as polythiophene, polyaniline or polyphenylene. The subject polymers allow assembly of the macromolecules in all three dimensions in the solid state. A ramification of the compact assembly is the realization of highly reflective, smooth coatings simply applied from solution. A preferred embodiment having a 1,3,5 hyperbranched polyphenylene core and poly (3-hexylthiophene) arms provides lustrous reflective gold coatings.

摘要翻译： 具有星形结构的导电聚合物包括具有多个附着位点的中心核心和从其辐射的共轭电荷输送臂。 核心衍生自具有多个附着位点的超支化聚合物，树枝状大分子或其它分子。 臂衍生自共轭低聚物和聚合物如聚噻吩，聚苯胺或聚亚苯基。 主题聚合物允许在固态下在所有三维中组装大分子。 紧凑型组件的分支是实现从溶液中简单应用的高反射，光滑的涂层。 具有1,3,5超支化聚亚苯基核和聚（3-己基噻吩）臂的优选实施方案提供光泽的反射金涂层。

公开(公告)号：US5956610A

公开(公告)日：1999-09-21

申请号：US861897

申请日：1997-05-22

申请人： William George En ,  Sunil Mehta ,  Fei Wang ,  Stewart Gordon Logie

发明人： William George En ,  Sunil Mehta ,  Fei Wang ,  Stewart Gordon Logie

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76895

摘要： The present invention provides a method and system for providing electrical insulation for local interconnect in a logic circuit. A system and method according to the present invention for providing electrical installation for local interconnects during manufacturing of a logic circuit comprising the steps of providing a first layer of material over a semiconductor wafer and providing a second layer of material over the first layer. Additionally, a photoresist material is provided over a portion of the logic circuit to be electrically insulated. Portions of the first and second layers which are unprotected by the photoresist material are then etched. At least a third layer is then provided over the first and second layers, and the third layer is etched such that the first layer as an electrical insulation over the portion of the logic circuit.

摘要翻译： 本发明提供了一种用于在逻辑电路中为局部互连提供电绝缘的方法和系统。 根据本发明的用于在制造逻辑电路期间为局部互连提供电气安装的系统和方法包括以下步骤：在半导体晶片上提供第一材料层，并在第一层上提供第二材料层。 另外，在逻辑电路的一部分上提供光电阻材料以进行电绝缘。 然后蚀刻由光致抗蚀剂材料未被保护的第一和第二层的部分。 然后在第一层和第二层上提供至少第三层，并且蚀刻第三层，使得第一层作为逻辑电路部分上的电绝缘。

公开(公告)号：US5895269A

公开(公告)日：1999-04-20

申请号：US993887

申请日：1997-12-18

申请人： Fei Wang ,  Minh Van Ngo ,  Darin A. Chan ,  David K. Foote ,  William G. En

发明人： Fei Wang ,  Minh Van Ngo ,  Darin A. Chan ,  David K. Foote ,  William G. En

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/28 ,  H01L21/3205

CPC分类号： H01L29/6659 ,  H01L21/76895

摘要： During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying dielectric layers. A punch-through region can damage the transistor circuit. In order to prevent punch-through, the oxide spacers are removed prior to forming an overlying dielectric layer.

摘要翻译： 在半导体晶片中局部互连的镶嵌形成期间，由于将与晶体管栅极相邻的氧化物间隔物暴露于用于蚀刻一个或多个蚀刻等离子体的一个或多个蚀刻等离子体，可以将穿透区域形成为衬底， 更重叠的电介质层。 穿通区域可能会损坏晶体管电路。 为了防止穿透，在形成覆盖的介电层之前去除氧化物间隔物。

公开(公告)号：US5288834A

公开(公告)日：1994-02-22

申请号：US36868

申请日：1993-03-25

申请人： Jacques Roovers ,  Fei Wang ,  Michael Guiver

发明人： Jacques Roovers ,  Fei Wang ,  Michael Guiver

IPC分类号： C08G61/12 ,  C08G65/48 ,  C08G8/02 ,  C08G14/00

CPC分类号： C08G61/127 ,  C08G65/48

摘要： Bromomethyl derivatives of polyaryl ether ketones are obtained by brominating methyl derivatives of the ketones preferably with elemental bromine, optionally under UV light. The bromomethyl derivatives are useful as intermediates for further functionalization of the aromatic polyether ketones. The functionalized derivatives, depending on the substituent, exhibit different properties than the basic polymer, for example increased hydrophilicity and solubility.

摘要翻译： 聚芳基醚酮的溴甲基衍生物可以通过溴化甲基衍生物，优选用元素溴，任选地在UV光下溴化。 溴甲基衍生物可用作芳族聚醚酮进一步官能化的中间体。 取决于取代基的官能化衍生物表现出与碱性聚合物不同的性质，例如增加的亲水性和溶解度。

公开(公告)号：US11353470B2

公开(公告)日：2022-06-07

申请号：US16726150

申请日：2019-12-23

申请人： Fei Wang ,  Qinhuangdao Water Bear Technology Co., Ltd.

发明人： Fei Wang

IPC分类号： G01N35/00 ,  G01N31/16

摘要： The present invention discloses a spectral-potentiometric-thermometric multi-dimensional titration analysis instrument, which comprises a spectral titration measurement device, a thermometric titration measurement device and a potentiometric titration measurement device which are arranged in parallel, meets the simultaneous measurement requirements of different analysis methods in chemical analysis, improves the measurement precision of different measurement methods, and effectively reduces the workload of separate experiments. The present invention further provides a usage method of the analysis instrument, provides analysis results of different angles and different characterization parameters for the change process of the material structure in the chemical reaction by conducting comparison analysis on data obtained using different measurement techniques, and effectively reduces the workload of titration analysis.

公开(公告)号：US20200087216A1

公开(公告)日：2020-03-19

申请号：US16557698

申请日：2019-08-30

申请人： Bai Cui ,  Fei Wang ,  Yongfeng Lu ,  Michael Nastasi

发明人： Bai Cui ,  Fei Wang ,  Yongfeng Lu ,  Michael Nastasi

IPC分类号： C04B41/00 ,  C04B41/45

摘要： Systems for and methods for improving mechanical properties of ceramic material are provided. The system comprises a heat source for heating the ceramic material to a temperature greater than a brittle-to-ductile transition temperature of the ceramic material; a probe for mounting the ceramic material and configured to extend the ceramic material into the heat source; a plasma-confining medium and a sacrificial layer disposed between the ceramic material and the plasma-confining medium; and an energy pulse generator such as a laser pulse generator. The sacrificial layer is utilized to form plasma between the ceramic material and the plasma-confining medium. The method comprises heating ceramic material to a temperature greater than a brittle-to-ductile transition temperature of the ceramic material and subjecting the ceramic material to energy pulses via a sacrificial layer and a plasma-confining medium whereby a plasma of the sacrificial coating forms between the ceramic material and a plasma-confining medium.

公开(公告)号：US20190206986A1

公开(公告)日：2019-07-04

申请号：US15076553

申请日：2016-03-21

申请人： Jun Hu ,  Zhiyun Luo ,  Fei Wang

发明人： Jun Hu ,  Zhiyun Luo ,  Fei Wang

IPC分类号： H01L29/06 ,  H01L21/266 ,  H01L21/761

CPC分类号： H01L29/0623 ,  H01L21/266 ,  H01L21/761 ,  H01L29/7811 ,  H01L29/7823

摘要： This invention discloses a semiconductor power device formed on a semiconductor substrate comprises an active cell area and a termination area disposed near edges of the semiconductor substrate. The termination area comprises a plurality of duplicated units wherein each unit includes at least two trenches filled with a conductive trench material having a mesa area between adjacent trenches wherein the trenches and the mesa areas within each of the duplicated units are electrically shunt together. In the termination area each of the trenches in the duplicated units has a buried guard ring dopant region disposed below a bottom surface of the trenches.