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公开(公告)号：US08179739B2
公开(公告)日：2012-05-15
申请号：US12672685
申请日：2007-08-10
IPC分类号： G11C8/00
CPC分类号： G11C5/06 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/74 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a select transistor (CT). A buffer cell is arranged between a sense amplifier (SA) and a memory cell array (MCA) and between a word driver (WDB) and the memory cell array. The buffer cell is formed of the resistive storage element (RE) and the select transistor (CT) same as those of the memory cell. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.
摘要翻译： 一种能够制造半导体器件的技术，而不会在涉及包括由可变电阻器和选择晶体管（CT）使用存储元件（RE）的存储器单元形成的存储单元阵列的相变存储器的制造设备中产生污染。 缓冲单元布置在读出放大器（SA）和存储单元阵列（MCA）之间以及字驱动器（WDB）和存储单元阵列之间。 缓冲单元由与存储单元相同的电阻存储元件（RE）和选择晶体管（CT）形成。 存储单元中的电阻存储元件通过形成在电阻存储元件上方的触点连接到位线。 同时，在缓冲单元中，电阻性存储元件之上不形成接触，并且在处理存储单元中的接触时保持被绝缘体覆盖的状态。 通过这种处理方法，可以避免在电阻存储元件中使用的硫族化物膜的曝光和升华。
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公开(公告)号：US08094489B2
公开(公告)日：2012-01-10
申请号：US13112567
申请日：2011-05-20
申请人： Satoru Hanzawa , Hitoshi Kume
发明人： Satoru Hanzawa , Hitoshi Kume
CPC分类号： G11C13/0023 , G11C13/0004 , G11C13/0026 , G11C13/0069 , G11C2013/0076 , G11C2013/0078 , G11C2013/0083 , G11C2213/71 , G11C2213/72
摘要： A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.
摘要翻译： 提供了具有高度可靠的操作的相变存储器。 半导体器件具有存储器阵列，其具有使用硫族化物材料和二极管层叠存储层的存储单元的结构，并且根据所选择的存储单元所在的层来改变初始化条件和写入条件。 初始化条件和写入条件（这里是复位条件）根据操作通过根据操作选择电流镜电路和通过电压选择电路和电流镜电路中的复位电流的控制机构而改变。
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公开(公告)号：US20110242872A1
公开(公告)日：2011-10-06
申请号：US13139297
申请日：2009-12-07
申请人： Satoru Hanzawa
发明人： Satoru Hanzawa
CPC分类号： G11C13/0069 , G11C7/18 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C2013/009 , G11C2213/71 , G11C2213/72
摘要： A highly-reliable, highly-integrated large-capacity phase-change memory is achieved. For this purpose, for example, memory tiles MT0, MT1 are provided respectively at points of intersection of global bit line GBL0 and global word lines GWL00B, GWL01B. Word lines WL000 of MT0, MT1 are commonly connected to an output from a word-line driving circuit WD0 which is controlled by GWL00B, and word lines WL001 of MT0, MT1 are commonly connected to an output from a word-line driving circuit WD1 controlled by GWL01B. For example, when WD0 is activated in accordance with a rewrite operation, an output from WD0 is connected to GBL0 via any one of four memory cells MC00, MC01 connected to WL000 of MT0, MT1.
摘要翻译： 实现了高度可靠，高度集成的大容量相变存储器。 为此，例如，分别在全局位线GBL0和全局字线GWL00B，GWL01B的交点处提供存储器片MT0，MT1。 MT0，MT1的字线WL000通常连接到由GWL00B控制的字线驱动电路WD0的输出，MT0，MT1的字线WL001共同连接到控制了字线驱动电路WD1的输出 由GWL01B。 例如，当根据重写操作激活WD0时，WD0的输出通过连接到MT0，MT1的WL000的四个存储单元MC00，MC01中的任一个连接到GBL0。
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公开(公告)号：US20110211390A1
公开(公告)日：2011-09-01
申请号：US12672685
申请日：2007-08-10
IPC分类号： G11C11/00 , H01L21/8239
CPC分类号： G11C5/06 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/74 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a select transistor (CT). A buffer cell is arranged between a sense amplifier (SA) and a memory cell array (MCA) and between a word driver (WDB) and the memory cell array. The buffer cell is formed of the resistive storage element (RE) and the select transistor (CT) same as those of the memory cell. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.
摘要翻译： 一种能够制造半导体器件的技术，而不会在涉及包括由可变电阻器和选择晶体管（CT）使用存储元件（RE）的存储器单元形成的存储单元阵列的相变存储器的制造设备中产生污染。 缓冲单元布置在读出放大器（SA）和存储单元阵列（MCA）之间以及字驱动器（WDB）和存储单元阵列之间。 缓冲单元由与存储单元相同的电阻存储元件（RE）和选择晶体管（CT）形成。 存储单元中的电阻存储元件通过形成在电阻存储元件上方的触点连接到位线。 同时，在缓冲单元中，电阻性存储元件之上不形成接触，并且在处理存储单元中的接触时保持被绝缘体覆盖的状态。 通过这种处理方法，可以避免在电阻存储元件中使用的硫族化物膜的曝光和升华。
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公开(公告)号：US07881088B2
公开(公告)日：2011-02-01
申请号：US12367108
申请日：2009-02-06
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.
摘要翻译： 有效存储范围指定的IP地址，以减少必要条目的数量，从而提高TCAM的存储容量。 本发明的代表性手段是：存储信息（条目）和输入信息（比较信息或搜索关键字）是公共块码，使得任何位必须是逻辑值“1”; 匹配线是分层结构的，并且存储器单元被布置在多个子匹配线和多条搜索线的交叉点处; 此外，子匹配线分别通过子匹配检测器连接到主匹配线，并且主匹配检测器被布置在主匹配线上。
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公开(公告)号：US20100214828A1
公开(公告)日：2010-08-26
申请号：US12377271
申请日：2006-09-15
申请人： Satoru Hanzawa , Yoshikazu Iida
发明人： Satoru Hanzawa , Yoshikazu Iida
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/004 , G11C2213/79
摘要： In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current. In order to achieve the object, the data bus occupation time in rewriting operation is shortened by using plural sense amplifiers and storing storage data temporarily, and plural programming circuits are provided and activated using the control signals with different phases. By the above, the phase change memory system with low current consumption can be realized, without causing degradation of the utilization ratio of the data bus.
摘要翻译： 在包括具有可变电阻的存储器件RQ和选择晶体管MQ的存储单元MC的存储器阵列MCA中，目的是在短时间内接收固定量的存储数据，并且实现对 存储单元，具有抑制的峰值电流。 为了实现该目的，通过使用多个读出放大器和临时存储存储数据来缩短重写操作中的数据总线占用时间，并且使用具有不同相位的控制信号来提供和激活多个编程电路。 通过上述，可以实现具有低电流消耗的相变存储器系统，而不会降低数据总线的利用率。
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公开(公告)号：US20100188877A1
公开(公告)日：2010-07-29
申请号：US12659984
申请日：2010-03-26
IPC分类号： G11C5/06
CPC分类号： H01L27/101 , G11C7/12 , G11C8/10 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/0054 , G11C2013/0078 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
摘要翻译： 本发明的目的是避免在由存储器单元组成的存储器阵列中驱动未选择的数据线，每个存储器单元在选择的字线上的所有存储单元中的选择晶体管时根据可变电阻使用存储元件和选择晶体管 进行。 为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。 由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。 因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。
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公开(公告)号：US20100073999A1
公开(公告)日：2010-03-25
申请号：US12445075
申请日：2006-10-12
申请人： Naoki Kitai , Satoru Hanzawa , Akira Kotabe
发明人： Naoki Kitai , Satoru Hanzawa , Akira Kotabe
IPC分类号： G11C7/00 , G11C11/00 , G11C11/419 , G11C13/00
CPC分类号： G11C11/419 , G11C7/065 , G11C13/0004 , G11C16/28 , G11C2013/0054 , G11C2213/82
摘要： In a readout circuit (RC) which detects a difference between a change that appears on a first signal line (CBL) and a change that appears on a second signal line (CBLdm) according to stored information of each selected memory cell, the first signal line and the second signal line are separated selectively from input nodes of a data latch circuit (DL) through second MOS transistors (MN3 and MN4) and capacitively coupled to the input nodes of the data latch circuit via gates of first MOS transistors (MP1 and MP2) respectively. In this separated state, the first and second signal lines and the input nodes of the data latch circuit are precharged to different voltages, so that the gate-to-source and drain-to-source voltages of the first MOS transistors are controlled by the voltages of the first and second signal lines respectively. Therefore, when the first and second signal lines are varied and the separated state is released upon a read operation, the first MOS transistors start to operate in a saturated region, thereby realizing a high-speed read operation.
摘要翻译： 在根据每个所选存储单元的存储信息检测出现在第一信号线（CBL）上的变化与出现在第二信号线（CBLdm）上的变化之间的差异的读出电路（RC）中，第一信号 线路和第二信号线通过第二MOS晶体管（MN3和MN4）选择性地从数据锁存电路（DL）的输入节点分离，并且经由第一MOS晶体管（MP1和...的栅极）电容耦合到数据锁存电路的输入节点 MP2）。 在这种分离状态下，数据锁存电路的第一和第二信号线和输入节点被预充电到不同的电压，使得第一MOS晶体管的栅极至源极和漏极到源极的电压由 分别是第一和第二信号线的电压。 因此，当第一和第二信号线变化并且在读取操作时释放分离状态时，第一MOS晶体管开始在饱和区域中工作，从而实现高速读取操作。
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公开(公告)号：US20090039335A1
公开(公告)日：2009-02-12
申请号：US12162769
申请日：2006-02-09
IPC分类号： H01L45/00
CPC分类号： H01L27/101 , G11C13/0004 , G11C13/0011 , G11C2213/79 , H01L27/0688 , H01L27/2436 , H01L27/2472 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/146 , H01L45/1625 , H01L45/1675
摘要： On an insulating film (31) in which a plug (35) is embedded, a second component releasing region (45) made of a first component and a second component, a solid electrolyte region (46) made of chalcogenide and an upper electrode region (47) are sequentially formed. The second component releasing region (45) made of a first component and a second component is composed of dome-shaped electrode portions (43) and an insulating film (44) burying the peripheries of the electrode portions (43), and at least one electrode portion (43) exists on the plug (34). The electrode portion (43) is composed of a first portion made of the first component such as tantalum oxide that is stable even when electric field is applied thereto and a second portion made of the second component such as copper or silver that is easily diffused in the solid electrolyte region (42) and moves therein by the application of an electric field. The second component supplied from the electrode portion (43) moves in the solid electrolyte region (46), thereby storing the information.
摘要翻译： 在其中嵌入有插塞（35）的绝缘膜（31）上，由第一部件和第二部件制成的第二部件释放区域（45），由硫族化物制成的固体电解质区域（46）和上部电极区域 （47）。 由第一部件和第二部件制成的第二部件释放区域（45）由埋入电极部分（43）的周边的圆顶状电极部分（43）和绝缘膜（44）组成，并且至少一个 电极部分（43）存在于插头（34）上。 电极部（43）由第一部分（例如氧化钽）构成的第一部分，即使施加电场也是稳定的，而由诸如铜或银的第二部分制成的第二部分容易扩散 固体电解质区域（42）并通过施加电场而在其中移动。 从电极部（43）供给的第二部件在固体电解质区域（46）中移动，从而存储信息。
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公开(公告)号：US20080062736A1
公开(公告)日：2008-03-13
申请号：US11976532
申请日：2007-10-25
IPC分类号： G11C5/02
CPC分类号： H01L27/101 , G11C7/12 , G11C8/10 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/0054 , G11C2013/0078 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
摘要翻译： 本发明的目的是避免在由选择的字线上的所有存储单元中的选择晶体管导通的存储单元中构成的存储器阵列中的未选择的数据线被驱动，每个存储器单元使用依赖于可变电阻的存储元件和选择晶体管 。 为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。 由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。 因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。
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