公开(公告)号：US07262101B2

公开(公告)日：2007-08-28

申请号：US10917294

申请日：2004-08-13

申请人： Dai Ishikawa ,  Satoshi Sakai ,  Atsushi Hiraiwa

发明人： Dai Ishikawa ,  Satoshi Sakai ,  Atsushi Hiraiwa

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/28185 ,  H01L21/0214 ,  H01L21/02332 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a semiconductor integrated circuit device comprising forming a silicon oxide film as thin as 5 nm or less on the surfaces of p type wells and n type wells by wet oxidizing a substrate, heating the substrate in an atmosphere containing about 5% of an NO gas to introduce nitrogen into the silicon oxide film so as to form a silicon oxynitride film, exposing the substrate to a nitrogen plasma atmosphere to further introduce nitrogen into the silicon oxynitride film in order to form a silicon oxynitride gate insulating film having a first peak concentration near the interface with the substrate and a second peak concentration near the surface thereof. Thereby, the concentration of nitrogen in the gate insulating film is increased without raising the concentration of nitrogen near the interface between the substrate and the gate insulating film to a higher level than required.

摘要翻译： 一种制造半导体集成电路器件的方法，包括在p型阱和n型阱的表面上通过湿式氧化衬底形成薄至5nm或更小的氧化硅膜，在含有约5％ 用于将氮气引入到氧化硅膜中以形成氧氮化硅膜的NO气体，将衬底暴露于氮等离子体气氛中，以进一步将氮气引入氮氧化硅膜中，以形成具有第一个氮氧化物的氮氧化硅栅极绝缘膜 与基板的界面附近的峰值浓度和其表面附近的第二峰值浓度。 由此，不会使衬底与栅极绝缘膜的界面附近的氮浓度提高到高于所需的水平，所以栅极绝缘膜的氮浓度增加。

公开(公告)号：US20070187764A1

公开(公告)日：2007-08-16

申请号：US11738741

申请日：2007-04-23

申请人： RYOICHI FURUKAWA ,  Satoshi Sakai ,  Satoshi Yamamoto

发明人： RYOICHI FURUKAWA ,  Satoshi Sakai ,  Satoshi Yamamoto

IPC分类号： H01L23/62

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.

摘要翻译： 在形成具有相同基板上的厚度相互不同的栅极绝缘膜的MISFET的过程中，抑制了在半导体基板和栅极绝缘膜之间的界面处形成不期望的自然氧化膜。 构成内部电路的MISFET的栅极绝缘膜由氮氧化硅膜构成。 构成I / O电路的MISFET的另一个栅极绝缘膜由层叠的氮氧化硅膜和高介电膜构成。 在多室系统的处理装置中连续地进行在基板上形成两种栅极绝缘膜的工序。 因此，基板不会暴露在空气中。 因此，可以抑制在基板和栅极绝缘膜之间的界面处包含不需要的异物和形成自然氧化膜。

公开(公告)号：US07211497B2

公开(公告)日：2007-05-01

申请号：US10695798

申请日：2003-10-30

申请人： Atsushi Hiraiwa ,  Satoshi Sakai ,  Dai Ishikawa ,  Yoshihiro Ikeda

发明人： Atsushi Hiraiwa ,  Satoshi Sakai ,  Dai Ishikawa ,  Yoshihiro Ikeda

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/3105 ,  H01L21/823857 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/513 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to the present invention, an oxide film with the film quality almost equivalent to that of the thermal oxide can be formed by the low-temperature treatment. After removing an insulator on the active region of the substrate which constitutes a semiconductor wafer, an insulator made of, for example, silicon oxide is deposited on the main surface of the semiconductor wafer by the low pressure CVD method. This insulator is a film to form a gate insulator of MISFET in a later step. Subsequently, a plasma treatment is performed in an atmosphere containing oxygen (oxygen plasma treatment) to the insulator in the manner as schematically shown by the arrows. By so doing, the film quality of the insulator formed by the CVD method can be improved to the extent almost equivalent to that of the insulator formed of the thermal oxide.

摘要翻译： 根据本发明，可以通过低温处理形成膜质量几乎等于热氧化物的氧化膜。 在构成半导体晶片的基板的有源区域上去除绝缘体之后，通过低压CVD法在半导体晶片的主表面上沉积由例如氧化硅制成的绝缘体。 该绝缘体是在后续步骤中形成MISFET的栅极绝缘体的膜。 随后，按照箭头示意性地示出的方式，在含有氧的气氛（氧等离子体处理）中对绝缘体进行等离子体处理。 通过这样做，通过CVD方法形成的绝缘体的膜质量可以提高到与由热氧化物形成的绝缘体几乎相同的程度。

公开(公告)号：US07109076B2

公开(公告)日：2006-09-19

申请号：US10855402

申请日：2004-05-28

申请人： Satoshi Sakai ,  Daichi Matsumoto ,  Katsuyuki Asaka ,  Masatoshi Hasegawa ,  Kazutaka Mori

发明人： Satoshi Sakai ,  Daichi Matsumoto ,  Katsuyuki Asaka ,  Masatoshi Hasegawa ,  Kazutaka Mori

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L27/10894 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116

摘要： Mutual diffusion of impurities in a gate electrode is suppressed near a boundary between an n-channel type MISFET and a p-channel type MISFET, which adopt a polycide's dual-gate structure. Since a gate electrode of an n-channel type MISFET and a gate electrode of a p-channel type MISFET are of mutually different conductivity types, they are separated to prevent the mutual diffusion of the impurities and are electrically connected to each other via a metallic wiring formed in the following steps. In a step before a gate electrode material is patterned to separate the gate electrodes, the mutual diffusion of the impurities before forming the gate electrodes is prevented by performing no heat treatment at a temperature of 700° C. or higher.

摘要翻译： 在n沟道型MISFET和p型沟道型MISFET之间的边界附近，抑制了栅电极中的杂质的相互扩散，其采用多选择性双栅结构。 由于n沟道型MISFET的栅电极和p沟道型MISFET的栅电极具有相互不同的导电类型，它们被分离以防止杂质的相互扩散，并且通过金属 布线按以下步骤形成。 在将栅电极材料图案化以分离栅电极之前的步骤中，通过在700℃以上的温度下不进行热处理来防止在形成栅电极之前杂质的相互扩散。

公开(公告)号：US20060121740A1

公开(公告)日：2006-06-08

申请号：US10519799

申请日：2002-08-15

申请人： Satoshi Sakai ,  Satoshi Yamamoto ,  Atsushi Hiraiwa ,  Ryoichi Furukawa

发明人： Satoshi Sakai ,  Satoshi Yamamoto ,  Atsushi Hiraiwa ,  Ryoichi Furukawa

IPC分类号： H01L21/469 ,  H01L21/31

CPC分类号： H01L29/513 ,  H01L21/823857

摘要： After forming a silicon oxide film 9 on the surface of a region A of a semiconductor substrate 1, a high dielectric constant insulating film 10, a silicon film, a silicon oxide film 14 are successively deposited over the semiconductor substrate 1, and they are patterned to leave the silicon oxide film 14 in regions for forming gate electrodes. Then, after fabricating silicon films 13n and 13p by using the patterned silicon oxide film 14 as a mask, when removing the silicon oxide film 14, etching is performed under the condition where the etching selectivity of the silicon oxide film 14 to the high dielectric constant insulating film 10 becomes large, thereby leaving the high dielectric constant insulating film 10 also to portions below the end of the gate electrodes (13n, 13p). Thus, it is possible to ensure the voltage withstanding thereof and improve the characteristics of MISFET.

摘要翻译： 在半导体衬底1的区域A的表面上形成氧化硅膜9之后，在半导体衬底1上依次沉积高介电常数绝缘膜10，硅膜，氧化硅膜14，并将其图案化 以将氧化硅膜14留在用于形成栅电极的区域中。 然后，通过使用图案化氧化硅膜14作为掩模来制造硅膜13 n和13 p之后，当去除氧化硅膜14时，在氧化硅膜14的蚀刻选择性高的条件下进行蚀刻 介电常数绝缘膜10变大，从而将高介电常数绝缘膜10也留在栅电极（13n，13p）的端部下方的部分。 因此，可以确保其耐受电压并改善MISFET的特性。

公开(公告)号：US07008880B2

公开(公告)日：2006-03-07

申请号：US10774588

申请日：2004-02-10

申请人： Yoshikazu Tanabe ,  Satoshi Sakai ,  Nobuyoshi Natsuaki

发明人： Yoshikazu Tanabe ,  Satoshi Sakai ,  Nobuyoshi Natsuaki

IPC分类号： H01L21/31

CPC分类号： H01L21/31662 ,  H01L21/02052 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31658 ,  H01L21/67109 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67213 ,  H01L21/67219 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/42364 ,  H01L29/518 ,  Y10S148/023 ,  Y10S148/116 ,  Y10S438/935

摘要： A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

公开(公告)号：US20050242379A1

公开(公告)日：2005-11-03

申请号：US10833998

申请日：2004-04-29

申请人： Satoshi Sakai ,  Shigenori Tsuruga ,  Hideo Yamakoshi ,  Shizuma Kuribayashi ,  Minoru Danno ,  Hiroshi Futami ,  Noriko Yamazaki

发明人： Satoshi Sakai ,  Shigenori Tsuruga ,  Hideo Yamakoshi ,  Shizuma Kuribayashi ,  Minoru Danno ,  Hiroshi Futami ,  Noriko Yamazaki

IPC分类号： B08B7/00 ,  B08B17/00 ,  G02B27/00 ,  H01L29/76

CPC分类号： G02B27/0006 ,  B08B7/0035 ,  B08B17/00 ,  G02B1/14

摘要： The objectives of the present invention are to prevent or inhibit the deterioration of optical systems that determine the longevity of an optical apparatus which delivers effects such as light transmission, diffraction, reflection, spectrum generation, and interference, and these combinations, and by so doing, decrease the frequency of maintenance operations such as window replacement and to reduce the costs for such operations. This invention is characterized by steps of creating a near vacuum zone with a presence of active energy to excite an oxidation reaction of carbon wherein the near vacuum zone faces the lighting surfaces of the optical system; generating negative ions or radicals in the near vacuum zone such as unstable chemical seeds containing oxygen atoms, such as OH radicals, OH− ions, ozone, O2− ions, O-radicals; and removing or reducing the accumulated carbon which deposits on the lighting surface, by reacting the deposited carbon with the negative ions or radicals. More specifically, the method according to this invention is characterized by the step of supplying active energy while supplying a flow of gases containing oxygen atoms such as water gas or oxidizing gas (for example, water vapor, oxygen, hydrogen peroxide, ozone or mixtures of said gases with inactive gases (including air)) into the near vacuum zone, thereby removing or reducing the accumulated carbon which deposits on the lighting surface by exciting the oxidation reaction of the accumulated carbon with the supplied active energy.

摘要翻译： 本发明的目的是防止或抑制光学系统的劣化，这些光学系统确定了传递诸如光透射，衍射，反射，光谱产生和干扰的效果的光学装置的寿命，以及这些组合。 ，减少窗户更换等维护操作的频率，降低这种操作的成本。 本发明的特征在于产生具有活性能量的近真空区以激发碳的氧化反应的步骤，其中近真空区面向光学系统的照明表面; 在近真空区域产生负离子或自由基，例如含有氧原子的不稳定的化学种子，例如OH基，OH - ，O 2 - ， - O - 离子，O-自由基; 以及通过使沉积的碳与负离子或自由基反应来除去或减少沉积在照明表面上的积累的碳。 更具体地说，根据本发明的方法的特征在于，在供给含有氧原子的气体流（例如水气或氧化气体（例如水蒸气，氧气，过氧化氢，臭氧或混合气体 所述具有惰性气体（包括空气）的气体）进入近真空区域，从而通过激发累积的碳与所提供的活性能的氧化反应去除或减少沉积在照明表面上的积聚的碳。

公开(公告)号：US20050205127A1

公开(公告)日：2005-09-22

申请号：US11028312

申请日：2005-01-04

申请人： Toshiya Watanabe ,  Nobuki Yamashita ,  Youji Nakano ,  Saneyuki Goya ,  Satoshi Sakai ,  Yoshimichi Yonekura

发明人： Toshiya Watanabe ,  Nobuki Yamashita ,  Youji Nakano ,  Saneyuki Goya ,  Satoshi Sakai ,  Yoshimichi Yonekura

IPC分类号： H01L21/28 ,  H01L31/0224 ,  H01L31/04 ,  H01L31/075 ,  H01L31/076 ,  H01L31/00

CPC分类号： H01L31/1884 ,  H01L31/022483 ,  H01L31/075 ,  H01L31/076 ,  Y02E10/548

摘要： A photovoltaic device is formed by depositing at least a first transparent electrode, PIN-structured or NIP-structured microcrystalline silicon layers, a second transparent electrode, and a back electrode in sequence on an electrically insulating transparent substrate. The PIN-structured or NIP-structured microcrystalline silicon layers include a p-type silicon layer, an i-type silicon layer, and an n-type silicon layer. At least one of the first transparent electrode and the second transparent electrode is a ZnO layer doped with Ga, and the Ga concentration is 15 atomic percent or less with respect to Zn.

摘要翻译： 通过在电绝缘透明基板上依次沉积至少第一透明电极，PIN结构或NIP结构的微晶硅层，第二透明电极和背电极来形成光电器件。 PIN结构或NIP结构的微晶硅层包括p型硅层，i型硅层和n型硅层。 第一透明电极和第二透明电极中的至少一个是掺杂有Ga的ZnO层，并且Ga相对于Zn为15原子％以下。

公开(公告)号：US20050045959A1

公开(公告)日：2005-03-03

申请号：US10496825

申请日：2001-11-30

申请人： Satoshi Sakai ,  Atsushi Hiraiwa ,  Satoshi Yamamoto

发明人： Satoshi Sakai ,  Atsushi Hiraiwa ,  Satoshi Yamamoto

IPC分类号： H01L21/8238 ,  H01L27/088 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L21/823462 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878

摘要： After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10) is formed on the semiconductor substrate (1). Consequently, two kinds of gate insulation films, namely, a gate insulation film (12) comprised of stacked film of high dielectric constant insulation film (10) and silicon oxide film (9) and gate insulation film (11) comprised of the high dielectric constant insulation film (10) are formed on the semiconductor substrate (1).

摘要翻译： 在半导体基板（1）的表面上形成氧化硅膜（9）之后，使用稀释的HF除去形成有效厚度小的栅极绝缘膜的区域中的氧化硅膜（9） 在半导体衬底（1）上形成高介电常数绝缘膜（10）。 因此，由高介电常数绝缘膜（10）和氧化硅膜（9）构成的栅极绝缘膜（12）和栅极绝缘膜（12）构成的两种栅极绝缘膜由高介电常数 在半导体衬底（1）上形成恒定绝缘膜（10）。

公开(公告)号：US06794257B2

公开(公告)日：2004-09-21

申请号：US10465642

申请日：2003-06-20

申请人： Dai Ishikawa ,  Satoshi Sakai ,  Atsushi Hiraiwa

发明人： Dai Ishikawa ,  Satoshi Sakai ,  Atsushi Hiraiwa

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/0214 ,  H01L21/02332 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a semiconductor integrated circuit device includes steps of forming a silicon oxide film as thin as 5 nm or less on the surfaces of p-type wells and n-type wells by wet oxidizing a substrate, heating the substrate in an atmosphere containing about 5% of an NO gas to introduce nitrogen into the silicon oxide film to form a silicon oxynitride film, and exposing the substrate to a nitrogen plasma atmosphere to further introduce nitrogen into the silicon oxynitride film to form a silcon oxynitride gate insulating film having a first peak concentration near the interface with the substrate and a second peak concentration near the surface thereof. Thereby, the concentration of nitrogen in the gate insulating film is increased without raising the concentration of nitrogen near the interface between the substrate and the gate insulating film to a higher level than required.

摘要翻译： 一种制造半导体集成电路器件的方法包括以下步骤：通过湿式氧化衬底，在p型阱和n型阱的表面上形成薄至5nm或更小的氧化硅膜，在包含 约5％的NO气体以将氮气引入到氧化硅膜中以形成氧氮化硅膜，并将衬底暴露于氮等离子体气氛中，以进一步将氮气引入到氧氮化硅膜中，以形成硅氧烷氮氧化物栅绝缘膜，其具有 与基板的界面附近的第一峰值浓度和其表面附近的第二峰值浓度。 由此，不会使衬底与栅极绝缘膜的界面附近的氮浓度提高到高于所需的水平，所以栅极绝缘膜的氮浓度增加。