公开(公告)号：US20050219893A1

公开(公告)日：2005-10-06

申请号：US11131384

申请日：2005-05-18

Applicant: Yasuhiko Tsukikawa ,  Takashi Ito

Inventor： Yasuhiko Tsukikawa ,  Takashi Ito

IPC: H01L27/108 ,  G11C7/18 ,  G11C11/401 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/02 ,  G11C11/24

CPC classification number: H01L27/10882 ,  G11C7/18 ,  G11C11/405 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10814

Abstract: Each cell unit has a cell plate electrically isolated from the cell plates in the other cell units.

Abstract translation: 每个电池单元具有与其它电池单元中的电池板电隔离的电池板。

公开(公告)号：US20050162894A1

公开(公告)日：2005-07-28

申请号：US11085213

申请日：2005-03-22

Applicant: Kiyoo Itoh ,  Kazuo Nakazato

Inventor： Kiyoo Itoh ,  Kazuo Nakazato

IPC: G11C11/404 ,  G11C11/405 ,  G11C11/4076 ,  G11C16/04 ,  G11C11/24

CPC classification number: G11C11/4076 ,  G11C11/404 ,  G11C11/405 ,  G11C16/0408 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A semiconductor integrated circuit device including a plurality of memory cells, each having a storage MOSFET holding information in a gate of the storage MOSFET, a write transistor supplying a write information voltage corresponding to the information to the gate storage MOSFET, and a capacitor having first and second terminals. Word lines and data lines are coupled with the memory cells. The first capacitor terminal is coupled with one of the word lines and the second capacitor terminal is coupled with the gate of the storage MOSFET. In a read operation of the semiconductor integrated circuit device, the gate voltage of the storage MOSFET is boosted by a transition of the word line from a first voltage to a second voltage greater than the first voltage.

Abstract translation: 一种半导体集成电路装置，包括多个存储单元，每个存储单元具有保存在存储MOSFET的栅极中的信息的存储MOSFET;写入晶体管，其将与该信息相对应的写入信息电压提供给栅极存储MOSFET;以及电容器，其具有第一 和第二终端。 字线和数据线与存储器单元耦合。 第一电容器端子与字线之一耦合，第二电容器端子与存储MOSFET的栅极耦合。 在半导体集成电路器件的读取操作中，通过字线从第一电压到大于第一电压的第二电压的转变来提高存储MOSFET的栅极电压。

公开(公告)号：US20050158951A1

公开(公告)日：2005-07-21

申请号：US11042495

申请日：2005-01-25

Applicant: Soon-kyou Jang

Inventor： Soon-kyou Jang

IPC: H01L27/10 ,  G11C11/405 ,  G11C11/406 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/336 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC classification number: H01L27/10894 ,  G11C11/405 ,  G11C11/406 ,  G11C11/40603 ,  H01L21/823462 ,  H01L27/10873

Abstract: Semiconductor memory devices include memory cell transistors having spaced apart memory cell transistor source and drain regions, and a memory cell transistor insulated gate electrode that includes a memory cell transistor gate dielectric layer. Refresh transistors also are provided that are connected to the memory cell transistor insulated gate electrodes and are configured to selectively apply negative bias to the memory cell transistor insulated gate electrodes in a refresh operation. The refresh transistors include spaced apart refresh transistor source and drain regions, and a refresh transistor insulated gate electrode. The refresh transistor insulated gate electrode includes a refresh transistor gate dielectric layer that is of different thickness that the memory cell transistor gate dielectric layer. The refresh transistor gate dielectric layer may be thinner than the memory cell transistor gate dielectric layer.

Abstract translation: 半导体存储器件包括具有间隔开的存储单元晶体管源极和漏极区域的存储单元晶体管，以及包括存储单元晶体管栅极介电层的存储单元晶体管绝缘栅电极。 还提供了刷新晶体管，其连接到存储单元晶体管绝缘栅电极，并且被配置为在刷新操作中选择性地向存储单元晶体管绝缘栅电极施加负偏压。 刷新晶体管包括间隔开的刷新晶体管源极和漏极区以及刷新晶体管绝缘栅电极。 刷新晶体管绝缘栅极包括与存储单元晶体管栅极介电层不同的厚度的刷新晶体管栅极介电层。 刷新晶体管栅极电介质层可以比存储单元晶体管栅极介电层薄。

公开(公告)号：US06894912B2

公开(公告)日：2005-05-17

申请号：US10760402

申请日：2004-01-21

Applicant: Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

Inventor： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4096 ,  G11C15/00 ,  G11C8/00

CPC classification number: G11C7/1051 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/405 ,  G11C11/4096 ,  G11C2207/107

Abstract: A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

公开(公告)号：US06891772B2

公开(公告)日：2005-05-10

申请号：US10804182

申请日：2004-03-19

Applicant: Paul Demone

Inventor： Paul Demone

IPC: G11C11/401 ,  G11C7/22 ,  G11C8/18 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C8/00

CPC classification number: G11C11/408 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/18 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

Abstract translation: 动态随机存取存储器（DRAM）执行读，写和刷新操作。 DRAM包括多个子阵列，每个子阵列具有多个存储器单元，每个存储单元与互补位线对和字线耦合。 DRAM还包括用于断言所选择的一条字线的字线使能装置和用于断言所选位线对之一的列选择装置。 提供了一种定时电路，用于响应于字线定时脉冲来控制字线使能装置，列选择装置以及读，写和刷新操作。 读取，写入和刷新操作在相同的时间内执行。

公开(公告)号：US20050088886A1

公开(公告)日：2005-04-28

申请号：US10979124

申请日：2004-11-03

Applicant: Yusuke Kanno ,  Kiyoo Itoh

Inventor： Yusuke Kanno ,  Kiyoo Itoh

IPC: G11C11/409 ,  G11C7/18 ,  G11C11/401 ,  G11C11/405 ,  G11C11/407 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C29/00

CPC classification number: G11C7/18 ,  G11C11/405 ,  G11C11/4097

Abstract: A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the memory in order to reduce the cost using a DRAM of a 3-transistor cell requiring no capacitor. A pair of data lines connected with a plurality of memory cells having the amplification function are set to different precharge voltage values, thereby eliminating the need of a dummy cell. The elimination of the need of the dummy cell unlike in the conventional DRAM circuit using a gain cell reduces both the required space and the production cost. A hierarchical structure of the data lines makes a high-speed operation possible. Also, a DRAM circuit can be fabricated through a fabrication process matched with an ordinary logic element.

Abstract translation: 公开了一种半导体集成电路，其中存储器以与安装有存储器的高速逻辑电路相当的高速度被激活，以便使用不需要电容器的3晶体管单元的DRAM来降低成本。 与具有放大功能的多个存储单元连接的一对数据线被设置为不同的预充电电压值，从而不需要虚设单元。 与使用增益单元的常规DRAM电路不同，消除虚设电池的需要减少了所需的空间和生产成本。 数据线的层次结构使得高速操作成为可能。 此外，可以通过与普通逻辑元件匹配的制造工艺来制造DRAM电路。

公开(公告)号：US20050087797A1

公开(公告)日：2005-04-28

申请号：US10985946

申请日：2004-11-12

Applicant: Tomoyuki Ishii ,  Kazuo Yano

Inventor： Tomoyuki Ishii ,  Kazuo Yano

IPC: H01L27/10 ,  B82B1/00 ,  G11C11/404 ,  G11C11/405 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788

CPC classification number: G11C11/405 ,  G11C11/404 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156

Abstract: A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.

Abstract translation: 半导体存储器件包括：第一晶体管，包括源极区，漏极区，形成在绝缘膜上并连接源极区和漏极区的半导体材料的第一沟道区;以及栅电极，用于控制第一 渠道区域 第二晶体管，包括源极区域，漏极区域，连接源极区域和漏极区域的半导体材料的第二沟道区域，用于控制第二沟道区域的电位的第二栅电极和与第二沟道区域耦合的电荷存储区域 第二通道区域通过静电容量; 其中所述第二晶体管的源极区域连接到源极线，所述第一晶体管的源极或漏极区域的一端连接到所述第二晶体管的电荷存储区域，所述源极或漏极区域的另一端 的第一晶体管连接到数据线。

公开(公告)号：US06882561B2

公开(公告)日：2005-04-19

申请号：US10649850

申请日：2003-08-26

Applicant: Kee-won Kwon ,  Su-jin Ahn

Inventor： Kee-won Kwon ,  Su-jin Ahn

IPC: G11C7/00 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/24

CPC classification number: G11C11/405 ,  G11C11/404 ,  G11C11/4091

Abstract: A semiconductor memory device includes a sense line, a data line, a memory connected between the sense line and the data line having an active restoration function, and a sense amplifier connected between the sense line and the data line. The sense amplifier senses and inverts the data in the sense line, and outputs the inverted data to the data line. The polarity of the data on the sense line is opposite the polarity of the data on the data line, and the data in the data line are written to the memory. The semiconductor memory device is capable of performing an active restoration function which makes it possible to rewrite the result of sensing operations from the sense amplifier without the need for an additional circuit or operations.

Abstract translation: 半导体存储器件包括检测线，数据线，连接在感测线和具有有效恢复功能的数据线之间的存储器，以及连接在检测线和数据线之间的读出放大器。 感测放大器感测并反转感测线中的数据，并将反相数据输出到数据线。 感测线上的数据的极性与数据线上的数据的极性相反，数据线中的数据被写入存储器。 半导体存储器件能够执行主动恢复功能，其使得可以从感测放大器重写感测操作的结果，而不需要额外的电路或操作。

公开(公告)号：US20050073871A1

公开(公告)日：2005-04-07

申请号：US10680348

申请日：2003-10-07

Applicant: Wing Luk ,  Robert Dennard

Inventor： Wing Luk ,  Robert Dennard

IPC: G11C11/405 ,  H01L27/108 ,  G11C11/24

CPC classification number: H01L27/108 ,  G11C11/405

Abstract: A random access memory (RAM) circuit is coupled to a write control line, a read control line, and one or more bitlines, and includes a write switch having a control terminal and first and second terminals. The first terminal of the write switch is coupled to the one or more bitlines, and the control terminal of the write switch is coupled to the write control line. The circuit includes a charge-storage device having first and second terminals, wherein a first terminal of the charge-storage device is coupled to the second terminal of the write switch and a second terminal of the charge-storage device is coupled to the read control line. The circuit includes a read switch having a control terminal and first and second terminals. The control terminal of the read switch is coupled to the first terminal of the charge-storage device and is coupled to the second terminal of the write switch. The first terminal of the read switch is coupled to the one or more bitlines, and the second terminal of the read switch coupled to ground. The circuit may be implemented through a number of disclosed semiconductor memory devices.

Abstract translation: 随机存取存储器（RAM）电路耦合到写入控制线，读取控制线和一个或多个位线，并且包括具有控制端子和第一和第二端子的写入开关。 写开关的第一端耦合到一个或多个位线，并且写开关的控制端耦合到写控制线。 该电路包括具有第一和第二端子的电荷存储装置，其中电荷存储装置的第一端子耦合到写入开关的第二端子，并且电荷存储装置的第二端子耦合到读取控制 线。 电路包括具有控制端子和第一和第二端子的读取开关。 读开关的控制端耦合到电荷存储装置的第一端并耦合到写开关的第二端。 读开关的第一端耦合到一个或多个位线，并且读开关的第二端耦合到地。 电路可以通过许多公开的半导体存储器件实现。

公开(公告)号：US06876569B2

公开(公告)日：2005-04-05

申请号：US10796023

申请日：2004-03-10

Applicant: Kiyoo Itoh ,  Kazuo Nakazato

Inventor： Kiyoo Itoh ,  Kazuo Nakazato

IPC: G11C11/404 ,  G11C11/405 ,  G11C11/4076 ,  G11C16/04 ,  G11C11/24

CPC classification number: G11C11/4076 ,  G11C11/404 ,  G11C11/405 ,  G11C16/0408 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A semiconductor integrated circuit device including a plurality of memory cells, each having a storage MOSFET holding information in a gate of the storage MOSFET, a write transistor supplying a write information voltage corresponding to the information to the gate storage MOSFET, and a capacitor having first and second terminals. Word lines and data lines are coupled with the memory cells. The first capacitor terminal is coupled with one of the word lines and the second capacitor terminal is coupled with the gate of the storage MOSFET. In a read operation of the semiconductor integrated circuit device, the gate voltage of the storage MOSFET is boosted by a transition of the word line from a first voltage to a second voltage greater than the first voltage.

Abstract translation: 一种半导体集成电路装置，包括多个存储单元，每个存储单元具有保存在存储MOSFET的栅极中的信息的存储MOSFET;写入晶体管，其将与该信息相对应的写入信息电压提供给栅极存储MOSFET;以及电容器，其具有第一 和第二终端。 字线和数据线与存储器单元耦合。 第一电容器端子与字线之一耦合，第二电容器端子与存储MOSFET的栅极耦合。 在半导体集成电路器件的读取操作中，通过字线从第一电压到大于第一电压的第二电压的转变来提高存储MOSFET的栅极电压。