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636 条记录 (耗时 0.026 秒)

    Buried digit line stack and process for making same
    91.
    发明申请
    Buried digit line stack and process for making same 有权
    埋地数字线堆栈和进程相同

    公开(公告)号：US20040029371A1

    公开(公告)日：2004-02-12

    申请号：US10636180

    申请日：2003-08-07

    申请人： Micron Technology, Inc.

    发明人： Y. Jeff Hu

    IPC分类号： H01L021/28

    CPC分类号： H01L23/53266 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76867 ,  H01L21/76889 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A process of making a buried digit line stack is disclosed. The process includes forming a silicon-lean metal silicide first film over a polysilicon plug, followed by a silicide compound barrier second film. The silicide compound barrier second film is covered with a refractory metal third film. A salicidation process causes the first film to salicide with the polysilicon plug. In one embodiment, all the aforementioned deposition processes are carried out by physical vapor deposition (nullPVDnull).

    摘要翻译： 公开了一种制作掩埋式数字线叠层的工艺。 该方法包括在多晶硅插塞上形成贫硅金属硅化物第一膜，随后是硅化合物屏障第二膜。 硅化物阻挡层第二膜被难熔金属第三膜覆盖。 水解过程使第一个膜与多晶硅插塞自杀。 在一个实施方案中，所有上述沉积工艺都是通过物理气相沉积（“PVD”）进行的。

    Buried digit line stack and process for making same
    94.
    发明授权
    Buried digit line stack and process for making same 有权
    埋地数字线堆栈和进程相同

    公开(公告)号：US06614116B1

    公开(公告)日：2003-09-02

    申请号：US10163289

    申请日：2002-06-04

    申请人： Y. Jeff Hu

    发明人： Y. Jeff Hu

    IPC分类号： H01L21461

    CPC分类号： H01L23/53266 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76867 ,  H01L21/76889 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A process of making a buried digit line stack is disclosed. The process includes forming a silicon-lean metal silicide first film over a polysilicon plug, followed by a silicide compound barrier second film. The silicide compound barrier second film is covered with a refractory metal third film. A salicidation process causes the first film to salicide with the polysilicon plug. In one embodiment, all the aforementioned deposition processes are carried out by physical vapor deposition (“PVD”).

    摘要翻译： 公开了一种制作掩埋式数字线叠层的工艺。 该方法包括在多晶硅插塞上形成贫硅金属硅化物第一膜，随后是硅化合物屏障第二膜。 硅化物阻挡层第二膜被难熔金属第三膜覆盖。 水解过程使第一个膜与多晶硅插塞自杀。 在一个实施方案中，所有上述沉积工艺都是通过物理气相沉积（“PVD”）进行的。

    Method of forming a crystalline phase material
    95.
    发明申请
    Method of forming a crystalline phase material 失效

    公开(公告)号：US20030095910A1

    公开(公告)日：2003-05-22

    申请号：US10300482

    申请日：2002-11-19

    发明人： Gurtej S. Sandhu ,  Sujit Sharan

    IPC分类号： C01B033/06 ,  B29C071/02

    CPC分类号： H01L21/02667 ,  C30B1/02 ,  C30B29/34 ,  H01L21/2022 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/32053 ,  H01L29/7842

    摘要： A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Where the compressive stress inducing material is provided on the opposite side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is greater than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix.

    Integrated circuit and method
    96.
    发明授权
    Integrated circuit and method 有权
    集成电路及方法

    公开(公告)号：US06528888B2

    公开(公告)日：2003-03-04

    申请号：US09776212

    申请日：2001-02-02

    申请人： Chih-Chen Cho ,  Jeffrey A. McKee ,  William R. McKee ,  Isamu Asano ,  Robert Y. Tsu

    发明人： Chih-Chen Cho ,  Jeffrey A. McKee ,  William R. McKee ,  Isamu Asano ,  Robert Y. Tsu

    IPC分类号： H01L2348

    CPC分类号： H01L27/10894 ,  H01L21/32051 ,  H01L21/32053 ,  H01L27/10811 ,  H01L27/10885

    摘要： An integrated circuit. The circuit includes a memory cell array including wordlines 201 formed on a substrate and bitlines 200 and capacitors 203 formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors 202 over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.

    摘要翻译： 集成电路。 电路包括存储单元阵列，其包括形成在基板上的字线201和位线200上形成的位线200和电容器203。 位线具有第一厚度和间距。 电路还包括阵列外围的电路，包括形成在衬底中的晶体管和晶体管上的导体202。 导体具有第二厚度和间距。 电路的特征还在于，位线和导体形成在公共导电层中。 在另外的实施例中，第一厚度和间距小于第二厚度和间距。

    CMOS self-aligned strapped interconnection
    98.
    发明授权
    CMOS self-aligned strapped interconnection 失效
    CMOS自对准绑扎互连

    公开(公告)号：US06388296B1

    公开(公告)日：2002-05-14

    申请号：US09257217

    申请日：1999-02-25

    申请人： Sheng Teng Hsu

    发明人： Sheng Teng Hsu

    IPC分类号： H01L2976

    CPC分类号： H01L21/32053 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823871

    摘要： An CMOS interconnection method that permits small source/drain surface areas has been provided. The interconnection is applicable to both strap and via type connections. The surface areas of the small source/drain regions are extended into neighboring field oxide regions by forming a silicide film from the source/drain regions to the field oxide. Interconnections on the same metal level, or to another metal level are made by contact to the silicide covered field oxide. The source/drain regions need only be large enough to accept the silicide film. Transistors with small source/drain regions have smaller drain leakage currents and less parasitic capacitance. A CMOS transistor interconnection apparatus has also been provided.

    摘要翻译： 已经提供了允许小的源/漏表面积的CMOS互连方法。 互连适用于带和通孔型连接。 通过从源极/漏极区域到场氧化物形成硅化物膜，将小的源极/漏极区域的表面积延伸到相邻的场氧化物区域。 通过与硅化物覆盖的场氧化物接触来制造相同金属层或另一金属层的互连。 源极/漏极区域仅需要足够大以接受硅化物膜。 具有较小源极/漏极区域的晶体管具有较小的漏极漏电流和较小的寄生电容。 还提供了CMOS晶体管互连装置。

    Semiconductor device having a metal silicide layer and method for manufacturing the same
    99.
    发明申请
    Semiconductor device having a metal silicide layer and method for manufacturing the same 有权
    具有金属硅化物层的半导体器件及其制造方法

    公开(公告)号：US20020036353A1

    公开(公告)日：2002-03-28

    申请号：US09949853

    申请日：2001-09-12

    发明人： Won-Sang Song ,  Jeong-Hwan Yang ,  In-Sun Park ,  Byoung-Moon Yoon

    IPC分类号： H01L029/06 ,  H01L027/01 ,  H01L023/48 ,  H01L029/40

    CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a semiconductor device having a metal suicide layer and a method for forming the metal silicide layer, the semiconductor device having a metal silicide-semiconductor contact structure, wherein the semiconductor device includes a substrate, an insulation layer with an opening, in which a metal silicide layer is formed using a native metal silicide with a first phase and a second phase, upon which a conductive layer is formed. The second phase has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. A reaction between the metal silicide layer of the first phase and the silicon results in the metal silicide layer of the second phase having high phase stability and low resistance.

    摘要翻译： 本发明提供一种具有金属硅化物层的半导体器件和用于形成金属硅化物层的方法，该半导体器件具有金属硅化物半导体接触结构，其中半导体器件包括衬底，具有开口的绝缘层， 使用具有第一相和第二相的天然金属硅化物形成金属硅化物层，在其上形成导电层。 第二相具有与第一相的第二化学计量组成比不同的第一化学计量组成比。 第一相的金属硅化物层与硅之间的反应导致第二相的金属硅化物层具有高相稳定性和低电阻。

    Semiconductor device and method of manufacturing the same
    100.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06359301B1

    公开(公告)日：2002-03-19

    申请号：US09103618

    申请日：1998-06-24

    申请人： Hideaki Kuroda

    发明人： Hideaki Kuroda

    IPC分类号： H01L27108

    CPC分类号： H01L27/10885 ,  H01L21/32053 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888 ,  H01L27/10894

    摘要： A semiconductor device comprising a first connecting plug for bit contact and a second connecting plug for storage node contact buried in a first inter-layer insulating layer covering the transistor and projecting from the transistor. The bit line is buried in a second inter-layer insulating layer and connected to the first connecting plug. The electrode of the storage node is partially buried in the second inter-layer insulating layer, connected on the second connecting plug, and projected above the second inter-layer insulating layer.

    摘要翻译： 一种半导体器件，包括用于位接触的第一连接插头和用于存储节点接触的第二连接插头，其掩埋在覆盖晶体管并从晶体管突出的第一层间绝缘层中。 位线被埋在第二层间绝缘层中并连接到第一连接插头。 存储节点的电极部分地埋在第二层间绝缘层中，连接在第二连接插头上，并突出在第二层间绝缘层之上。