公开(公告)号：US07453325B2

公开(公告)日：2008-11-18

申请号：US10917101

申请日：2004-08-12

Applicant: Markus Hammes ,  Giuseppe Li Puma ,  Stefan Van Waasen

Inventor： Markus Hammes ,  Giuseppe Li Puma ,  Stefan Van Waasen

IPC: H03C3/09 ,  H03L7/18

CPC classification number: H03C3/0933 ,  H03C3/0925 ,  H03L7/1976

Abstract: A single-point modulator (1) has a PLL circuit (2) and a programmable frequency divider (7) whose control connection is connected to a circuit branch for injecting a digital modulation signal (15) which is arranged in the feedback path of the PLL circuit (2). The circuit branch contains a sigma-delta modulator (9) which, in turn, has a digital filter (24) having a transfer function H(z). The noise transfer function NTF(z) of the sigma-delta modulator (9) is given by the function NTF(z)=1−H(z).

Abstract translation: 单点调制器（1）具有PLL电路（2）和可编程分频器（7），其控制连接连接到电路支路，用于注入数字调制信号（15），该数字调制信号（15）被布置在 PLL电路（2）。 电路分支包含一个Σ-Δ调制器（9），它又具有一个具有传递函数H（z）的数字滤波器（24）。 Σ-Δ调制器（9）的噪声传递函数NTF（z）由函数NTF（z）= 1-H（z）给出。

公开(公告)号：US07417513B2

公开(公告)日：2008-08-26

申请号：US11208237

申请日：2005-08-17

Applicant: Walid Khairy Mohamed Ahmed ,  David Bengtson

Inventor： Walid Khairy Mohamed Ahmed ,  David Bengtson

IPC: H03C3/06

CPC classification number: H03L7/1976 ,  H03C3/0925 ,  H03C3/0933 ,  H03L7/093

Abstract: A system and method for modulating a phase component of an electromagnetic signal includes a phase/frequency detector having first and second inputs and an output. The first phase/frequency detector input may be configured to receive a reference signal. The system may include an oscillator having an input and an output. The oscillator may be configured to generate a desired oscillator output signal at its output. A divider may be configured to receive the oscillator output signal. The divider may have a divider count input and a divider carryout output that may be connected to the second phase/frequency detector input. A loop filter may be connected in series between the phase/frequency detector output and the oscillator input. The loop filter has a transfer function including at least two frequency response rate change points, where each of the frequency rate change points corresponds to a pole or a zero in the transfer function.

Abstract translation: 用于调制电磁信号的相位分量的系统和方法包括具有第一和第二输入和输出的相位/频率检测器。 第一相/频率检测器输入可以被配置为接收参考信号。 该系统可以包括具有输入和输出的振荡器。 振荡器可以被配置为在其输出端产生期望的振荡器输出信号。 分频器可以被配置为接收振荡器输出信号。 分频器可以具有分频器计数输入和可以连接到第二相位/频率检测器输入的分频器输出输出。 环路滤波器可以串联连接在相位/频率检测器输出和振荡器输入之间。 环路滤波器具有包括至少两个频率响应速率变化点的传递函数，其中每个频率变化点对应于传递函数中的极点或零点。

公开(公告)号：US07405629B2

公开(公告)日：2008-07-29

申请号：US11172691

申请日：2005-06-30

Applicant: Shuliang Li

Inventor： Shuliang Li

IPC: H03M3/02

CPC classification number: H03C3/0933 ,  H03C3/0925

Abstract: A frequency synthesizer is provided having a fractional-N control circuit and method. The control circuit can operate as having a modulator that selectively applies any fractional ratio to a frequency divider within, for example, a feedback loop of a PLL. The modulator can be a delta-sigma modulator or any sequential state machine that can be implemented as the control circuit, and can select amongst a plurality of vector values. The vector values can be spaced relatively close to each other, and the incoming present vector values can each be added to a value chosen from the immediately preceding set of potential values. The selector circuit chooses from among the present set of vector values depending on whether the sum is nearest a target value. The sum nearest the target value is, therefore, selected as the present vector value, and the process is repeated in time for each vector value having a corresponding P value to form a pattern of P values sent to the divider of the PLL. The incoming frequency can therefore be synthesized based on the modulated P values used by the feedback divider to produce the appropriate fractional-N divide ratio for the synthesized frequency.

Abstract translation: 提供了具有分数N控制电路和方法的频率合成器。 控制电路可以作为具有选择性地将任何分数比率应用于例如PLL的反馈环路内的分频器的调制器。 调制器可以是Δ-Σ调制器或可以被实现为控制电路的任何顺序状态机，并且可以在多个向量值中进行选择。 向量值可以彼此相对接近地间隔开，并且输入的当前向量值可以各自被添加到从紧接在前的潜在值集合中选择的值。 选择器电路根据总和是否最接近目标值，从当前矢量值集中选择。 因此，最接近目标值的和被选择为当前向量值，并且对于具有相应P值的每个向量值，时间上重复处理，以形成发送到PLL的分频器的P值的模式。 因此，可以基于由反馈分频器使用的调制P值来合成输入频率，以产生合成频率的适当的分数N分频比。

公开(公告)号：US07289004B2

公开(公告)日：2007-10-30

申请号：US11204141

申请日：2005-08-15

Applicant: Evelyn L Chan ,  Fuad Haji Mokhtar ,  Ann Yen Lim

Inventor： Evelyn L Chan ,  Fuad Haji Mokhtar ,  Ann Yen Lim

IPC: H03C3/09

CPC classification number: H03C3/0925 ,  H03C3/08 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0975 ,  H03C3/20

Abstract: The present invention relates generally to the field of frequency modulation, and in particular to dual port frequency modulators. The present invention provides a frequency modulator comprising a phase lock loop circuit (108) for receiving and modulating a carrier signal according to the low frequency component of a modulating signal, the phase lock loop circuit comprising a voltage controlled oscillator (118) for outputting a modulated carrier signal and a loop filter (116) for outputting a steering voltage to the VCO, the VCO having a tank circuit (120) comprising a voltage controlled capacitance (VAR1). The frequency modulator also comprises an external voltage controlled capacitance (122) which is arranged to modulate its capacitance according to a high frequency component of the modulating signal, the second voltage controlled capacitance being coupled to the tank circuit. The phase lock loop circuit (108) is further arranged to modulate the steering voltage to the VCO (118) with the high frequency component of the modulating signal.

Abstract translation: 本发明一般涉及频率调制领域，特别涉及双端口频率调制器。 本发明提供了一种频率调制器，其包括用于根据调制信号的低频分量接收和调制载波信号的锁相环电路（108），所述锁相环电路包括用于输出调制信号的压控振荡器（118） 调制载波信号和用于向VCO输出转向电压的环路滤波器（116），所述VCO具有包括压控电容（VAR 1）的振荡电路（120）。 频率调制器还包括外部电压控制电容（122），其被布置成根据调制信号的高频分量调制其电容，第二压控电容耦合到储能电路。 锁相环电路（108）还被布置成用调制信号的高频分量调制到VCO（118）的转向电压。

公开(公告)号：US20070236297A1

公开(公告)日：2007-10-11

申请号：US11626585

申请日：2007-01-24

Applicant: Toshiya UOZUMI ,  Jiro Shimbo

Inventor： Toshiya UOZUMI ,  Jiro Shimbo

IPC: H03L7/00

CPC classification number: H03L7/1976 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03L7/07

Abstract: A level converter level-converts an oscillation output signal of a reference frequency oscillator and supplies the level-converted signal to a phase comparator of a PLL/fractional synthesizer for controlling an oscillation frequency of an RF transmission voltage-controlled oscillator. The level converter includes a self-bias type voltage amplifier which amplifies a reference frequency signal of the reference frequency oscillator. The self-bias type voltage amplifier includes a coupling capacitor, an amplifying transistor, a load and a bias element and suppresses a variation in the level of each harmonic component even though an external power supply voltage varies.

Abstract translation: 电平转换器电平转换参考频率振荡器的振荡输出信号，并将电平转换信号提供给PLL /分数合成器的相位比较器，用于控制RF发射压控振荡器的振荡频率。 电平转换器包括放大参考频率振荡器的参考频率信号的自偏置型电压放大器。 自偏置型电压放大器包括耦合电容器，放大晶体管，负载和偏置元件，并且即使外部电源电压变化也抑制每个谐波分量的电平变化。

公开(公告)号：US07259633B2

公开(公告)日：2007-08-21

申请号：US11137210

申请日：2005-05-24

Applicant: Chang-Hyeon Lee ,  Akbar Ali

Inventor： Chang-Hyeon Lee ,  Akbar Ali

IPC: H03L7/00 ,  H03L7/093

CPC classification number: H03L7/093 ,  H03C3/0925 ,  H03C3/0933 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/197 ,  H03L7/1976

Abstract: According to one exemplary embodiment, a frequency synthesizer module includes a loop filter, where the loop filter includes a capacitor having a first terminal and a second terminal. The frequency synthesizer module further includes a loop filter calibration module coupled to the capacitor in the loop filter. The loop filter calibration module causes an initial capacitance between the first terminal and the second terminal of the capacitor to increase to a target capacitance when the loop filter is in a calibration mode. The target capacitance can causes in increase in control of a bandwidth of the loop filter and a reduction in percent error of a unity gain bandwidth of the loop filter. The loop filter further includes a switched capacitor array configured to cause the initial capacitance to increase to the target capacitance in response to a digital feedback signal provided by the loop filter calibration module.

Abstract translation: 根据一个示例性实施例，频率合成器模块包括环路滤波器，其中环路滤波器包括具有第一端子和第二端子的电容器。 频率合成器模块还包括耦合到环路滤波器中的电容器的环路滤波器校准模块。 当环路滤波器处于校准模式时，环路滤波器校准模块使得电容器的第一端子和第二端子之间的初始电容增加到目标电容。 目标电容可以导致环路滤波器的带宽的控制的增加和环路滤波器的单位增益带宽的百分比误差的减小。 环路滤波器还包括开关电容器阵列，其被配置为响应于由环路滤波器校准模块提供的数字反馈信号而使初始电容增加到目标电容。

公开(公告)号：US20070189431A1

公开(公告)日：2007-08-16

申请号：US11675573

申请日：2007-02-15

Applicant: Khurram Waheed ,  Tim Foo ,  Robert B. Staszewski

Inventor： Khurram Waheed ,  Tim Foo ,  Robert B. Staszewski

IPC: H03D3/24 ,  H04L27/04

CPC classification number: H04L27/3818 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966 ,  H03C3/0991 ,  H03C5/00 ,  H03L2207/50

Abstract: A novel apparatus for and method of delay alignment in a closed loop two-point modulation all digital phase locked loop (ADPLL). The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison. Within the ADPLL portion of the transmitter, precise alignment of reference and direct point injection points in the ADPLL is provided using multiple clock domains, tapped delay lines and clock adjustment circuits.

Abstract translation: 一种闭环双点调制全数字锁相环（ADPLL）的延迟对准的新颖设备和方法。 本发明提供了一种全数字延迟对准机构，其通过考虑发射机的数字电路模块中的处理延迟以及通过使用分布在几个时钟域上的可编程延迟元件来实现比纳秒对准更好的方法。 分接延迟线补偿模拟元件（如DCO，分频器，四通道开关，缓冲器，电平移位器和数字预功率放大器（DPA））中的传播和稳定延迟。 提供了一种信号相关机制，其中来自要匹配的幅度和相位/频率调制路径的数据首先被内插，然后进行交叉相关，以获得比时钟域更好的比较。 在发射机的ADPLL部分内，使用多个时钟域，抽头延迟线和时钟调整电路提供ADPLL中的参考点和直接点注入点的精确对准。

公开(公告)号：US20070164828A1

公开(公告)日：2007-07-19

申请号：US11727216

申请日：2007-03-26

Applicant: Toshiya Uozumi ,  Yasuyuki Kimura ,  Hirotaka Osawa ,  Satoru Yamamoto ,  Robert Henshaw

Inventor： Toshiya Uozumi ,  Yasuyuki Kimura ,  Hirotaka Osawa ,  Satoru Yamamoto ,  Robert Henshaw

IPC: H03L7/00

CPC classification number: H04B1/04 ,  H03C3/0925 ,  H03C3/0933 ,  H03D7/165 ,  H03D2200/0047 ,  H03J1/005 ,  H03L7/1976

Abstract: In a communication semiconductor integrated circuit device using offset PLL architectures and including an oscillator circuit and a frequency divider circuit generating an intermediate frequency signal, the oscillator circuit includes an oscillator, a programmable frequency divider which frequency-divides the oscillation signal in accordance with frequency division information, a phase comparator detecting a phase difference between an output signal of the programmable frequency divider and a reference signal, and a frequency control unit for outputting a signal indicative of the phase difference and controlling the oscillation frequency of the oscillator, wherein a frequency division ratio generator circuit generates an integer part I and a fraction part F/G based on band information concerning the use frequency band and mode information along with channel information and for producing the frequency division ratio information to thereby give it to the programmable frequency divider.

公开(公告)号：US07205850B2

公开(公告)日：2007-04-17

申请号：US11181876

申请日：2005-07-15

Applicant: Toshiya Uozumi ,  Yasuyuki Kimura ,  Hirotaka Osawa ,  Satoru Yamamoto ,  Robert Astel Henshaw

Inventor： Toshiya Uozumi ,  Yasuyuki Kimura ,  Hirotaka Osawa ,  Satoru Yamamoto ,  Robert Astel Henshaw

IPC: H03L7/18

CPC classification number: H04B1/04 ,  H03C3/0925 ,  H03C3/0933 ,  H03D7/165 ,  H03D2200/0047 ,  H03J1/005 ,  H03L7/1976

Abstract: In a communication semiconductor integrated circuit device using offset PLL architectures and including an oscillator circuit and a frequency divider circuit generating an intermediate frequency signal, the oscillator circuit includes an oscillator, a programmable frequency divider which frequency-divides the oscillation signal in accordance with frequency division information, a phase comparator detecting a phase difference between an output signal of the programmable frequency divider and a reference signal, and a frequency control unit for outputting a signal indicative of the phase difference and controlling the oscillation frequency of the oscillator, wherein a frequency division ratio generator circuit generates an integer part I and a fraction part F/G based on band information concerning the use frequency band and mode information along with channel information and for producing the frequency division ratio information to thereby give it to the programmable frequency divider.

公开(公告)号：US07180385B2

公开(公告)日：2007-02-20

申请号：US10939587

申请日：2004-09-13

Applicant: Christian Grewing ,  Markus Hammes ,  André Hanke ,  Stefan Van Waasen

Inventor： Christian Grewing ,  Markus Hammes ,  André Hanke ,  Stefan Van Waasen

IPC: H03C3/06

CPC classification number: H03C3/0983 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/40

Abstract: A transmission arrangement includes a step-up frequency mixer that converts a modulation signal to a transmission frequency. The step-up frequency mixer is arranged within a phase locked loop that further comprises a frequency divider that is likewise supplied with the modulation data, combined with channel pre-selection data, for the purposes of compensation. This arrangement prevents low-frequency components of the modulation signal from being eliminated by the phase locked loop. In addition, noise components and undesirable interference frequency components that are produced in the mixer are suppressed by the phase locked loop.

Abstract translation: 传输装置包括将调制信号转换为传输频率的升压混频器。 升压型混频器被布置在锁相环内，该锁相环还包括分频器，该分频器同样被提供调制数据，与通道预选数据相结合，用于补偿。 这种布置防止了调制信号的低频分量被锁相环消除。 此外，在混频器中产生的噪声分量和不期望的干扰频率分量被锁相环抑制。