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    Logic gate having low power consumption
    92.
    发明授权
    Logic gate having low power consumption 失效
    逻辑门具有低功耗

    公开(公告)号：US4755695A

    公开(公告)日：1988-07-05

    申请号：US893496

    申请日：1986-08-05

    申请人： Tomihiro Suzuki

    发明人： Tomihiro Suzuki

    IPC分类号： H03K19/0185 ,  H01L27/095 ,  H01L29/41 ,  H03K19/017 ,  H03K19/0952 ,  H03K3/26 ,  H03K17/16 ,  H03K19/094

    CPC分类号： H03K19/01714 ,  H03K19/0952

    摘要： A semiconductor logic circuit device uses a plurality of MESFETs and a Schottky barrier diode (11) interconnected in such a way that one MESFET forms a switching input (9), another MESFET may form a load (8), still another MESFET forms a buffer amplifier stage (10), a further MESFET forms a current source, and the Schottky barrier diode operates as a speed-up capacitor for increasing the response characteristic of the buffer stage. Different types of logic circuits may be formed.

    摘要翻译： 半导体逻辑电路器件使用以一个MESFET形成开关输入（9）的方式互连的多个MESFET和肖特基势垒二极管（11），另一个MESFET可以形成负载（8），另一个MESFET形成缓冲器 放大器级（10），另一个MESFET形成电流源，肖特基势垒二极管用作加速电容器，用于增加缓冲级的响应特性。 可以形成不同类型的逻辑电路。

    Semiconductor device
    93.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4628338A

    公开(公告)日：1986-12-09

    申请号：US779618

    申请日：1985-09-25

    申请人： Yoshiro Nakayama ,  Hidetake Suzuki

    发明人： Yoshiro Nakayama ,  Hidetake Suzuki

    IPC分类号： H01L21/28 ,  H01L21/338 ,  H01L23/485 ,  H01L27/095 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/80 ,  H01L29/812 ,  H01L29/48

    CPC分类号： H01L29/452 ,  H01L23/485 ,  H01L29/475 ,  H01L29/80 ,  H01L2924/0002

    摘要： A compact connection structure between two electrodes made of two types of metals, i.e., metals which respectively make Schottky and ohmic contact with a semiconductor, is provided by using a high melting point metal or silicide thereof which makes Schottky contact with the semiconductor as one electrode metal. The two types of electrodes can be brought into direct contact with each other, enabling elimination of through hole connections between them and therefore increased semiconductor device density.

    摘要翻译： 通过使用高熔点金属或硅化物提供由两种类型的金属制成的紧密连接结构，即分别制造肖特基和欧姆接触半导体的金属，其使得肖特基与半导体作为一个电极接触 金属。 两种类型的电极可以彼此直接接触，从而能够消除它们之间的通孔连接并因此提高半导体器件密度。

    Self-aligned MESFETs having reduced series resistance
    95.
    发明授权
    Self-aligned MESFETs having reduced series resistance 失效
    具有降低的串联电阻的自对准MESFET

    公开(公告)号：US4304042A

    公开(公告)日：1981-12-08

    申请号：US171617

    申请日：1980-07-23

    申请人： Keming W. Yeh

    发明人： Keming W. Yeh

    IPC分类号： H01L21/033 ,  H01L21/338 ,  H01L21/8234 ,  H01L27/095 ,  H01L29/812 ,  H01L21/26

    CPC分类号： H01L29/66848 ,  H01L21/033 ,  H01L21/8234 ,  H01L27/095 ,  H01L29/812

    摘要： Disclosed herein is a structure and process for a self-aligned metal semiconductor field effect transistor having the characteristics of a high speed, high density, low power LSI circuit and specifically an improved high device gain MESFET device using conventional photographic techniques. The inventive MESFET device has improved high device gain as a result of the elimination of series resistance, increased circuit integration density, and improved speed capability due to the elimination of spacings between gate and drain and gate and source and the improved high device gain.CROSS REFERENCE TO RELATED APPLICATION

    摘要翻译： 本文公开了具有高速，高密度，低功率LSI电路的特性的自对准金属半导体场效应晶体管的结构和工艺，特别是使用传统照相技术的改进的高器件增益MESFET器件。 本发明的MESFET器件由于消除了栅极和漏极以及栅极和源极之间的间隔以及改进的高器件增益而由于消除串联电阻，增加的电路集成密度和改进的速度能力而提高了器件的增益。

    III-V SEMICONDUCTOR DEVICE WITH INTEGRATED POWER TRANSISTOR AND START-UP CIRCUIT
    98.
    发明申请
    III-V SEMICONDUCTOR DEVICE WITH INTEGRATED POWER TRANSISTOR AND START-UP CIRCUIT 有权

    公开(公告)号：US20230050918A1

    公开(公告)日：2023-02-16

    申请号：US17977290

    申请日：2022-10-31

    申请人： Cambridge GaN Devices Limited

    发明人： Florin UDREA ,  Loizos EFTHYMIOU

    IPC分类号： H01L27/095 ,  H03K17/687 ,  H02M3/335 ,  H02M1/36 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/8252 ,  H01L29/66

    摘要： We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on the substrate. The second heterojunction transistor comprises: a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas; a third terminal operatively connected to the second III-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in the first dimension and operatively connected to the second III-nitride semiconductor region; a second gate region being formed over the second III-nitride semiconductor region, and between the third terminal and the fourth terminal. One of the first and second heterojunction transistors is an enhancement mode field effect transistor and the other of the first and second heterojunction transistors is a depletion mode field effect transistor.

    III-V SEMICONDUCTOR DEVICE WITH INTEGRATED PROTECTION FUNCTIONS
    99.
    发明申请
    III-V SEMICONDUCTOR DEVICE WITH INTEGRATED PROTECTION FUNCTIONS 有权

    公开(公告)号：US20220208761A1

    公开(公告)日：2022-06-30

    申请号：US17609368

    申请日：2020-05-07

    申请人： CAMBRIDGE GAN DEVICES LIMITED

    发明人： Florin Udrea ,  Loizos Efthymiou ,  Giorgia Longobardi ,  Martin Arnold

    IPC分类号： H01L27/088 ,  H01L27/06 ,  H01L27/095 ,  H03K17/082

    摘要： We disclose a Ill-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor (19) formed on a substrate, the first heterojunction transistor comprising: a first Ill-nitride semiconductor region formed over the substrate, wherein the first Ill-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal (8) operatively connected to the first Ill-nitride semiconductor region; a second terminal (9) laterally spaced from the first terminal and operatively connected to the first Ill-nitride semiconductor region; a first gate terminal (10) formed over the first Ill-nitride semiconductor region between the first terminal and the second terminal. The device also includes a second heterojunction transistor (14) formed on a substrate, the second heterojunction transistor comprising: a second Ill-nitride semiconductor region formed over the substrate, wherein the second Ill-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a third terminal operatively connected to the second Ill-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in a first dimension and operatively connected to the second Ill-nitride semiconductor region, wherein the fourth terminal is operatively connected to the first gate terminal; and a second gate terminal formed over the second Ill-nitride semiconductor region between the third terminal and the fourth terminal and wherein the second heterojunction transistor is used in sensing and protection functions of the first power heterojunction transistor. The device also includes at least one monolithically integrated current sensing transistor (16) that has a substantially identical structure to the first heterojunction transistor, and
    wherein the third transistor is scaled to a smaller area or a shorter gate width when compared to the first heterojunction transistor by a scale factor, X, where X is larger than 1. Other embodiments include both internal and external sensing, sensing loads and a feedback circuit to provide overcurrent, gate over-voltage or over-temperature protection.