公开(公告)号：US20150061769A1

公开(公告)日：2015-03-05

申请号：US14464611

申请日：2014-08-20

Applicant: Analog Devices Technology

Inventor： Rares Andrei Bodnar ,  Patrick Joseph Pratt ,  Donal Bourke ,  Peter James Tonge

IPC: H03G3/30 ,  H03F3/21 ,  H03G3/00 ,  H03F3/193

CPC classification number: H03G3/3042 ,  H03F1/301 ,  H03F1/3205 ,  H03F3/193 ,  H03F3/21 ,  H03F2200/129 ,  H03F2200/144 ,  H03F2200/18 ,  H03F2200/451 ,  H03F2200/462 ,  H03F2200/481 ,  H03G3/001 ,  H03G3/3089

Abstract: A control apparatus is provided that can provide high dynamic resolution and is suitable for inclusion within an integrated circuit. The control apparatus receives a demand signal representing a desired value of a measurand, and a feedback signal representing a present value or a recently acquired value of the measurand. The processing circuit forms a further signal a further signal which is a function of the demand and feedback signals. The further signal is then subjected to at least an integrating function. The demand signal, feedback signal or the further signal is processed or acquired in a sampled manner. The use of such sampled, i.e. discontinuous, processing allows integration time constants to be synthesized which would otherwise require the use of unfeasibly large components within an integrated circuit, or the use of off-chop components. Both of these other options are expensive.

Abstract translation: 提供了能够提供高动态分辨率并且适合于包含在集成电路内的控制装置。 控制装置接收表示被测量的期望值的需求信号，以及表示被测量的当前值或最近获取的值的反馈信号。 处理电路形成另外的信号，该信号是需求和反馈信号的函数。 然后进一步的信号经受​​至少一个积分函数。 以采样方式处理或获取需求信号，反馈信号或进一步的信号。 使用这种采样，即不连续的处理允许合成的积分时间常数，否则这将需要在集成电路内使用不可行的大部件，或者使用不合格的部件。 这些其他选项都是昂贵的。

公开(公告)号：US20150016567A1

公开(公告)日：2015-01-15

申请号：US13940263

申请日：2013-07-12

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Dong Chen

IPC: H04B1/04

CPC classification number: H04B1/0475 ,  H03F1/3247 ,  H03F1/3258 ,  H03F1/3282 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/111 ,  H03F2201/3206 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H04B2001/0425

Abstract: Various digital pre-distortion systems for use in transmitters are disclosed. The digital pre-distortion system comprises an observing path, which performs either undersampling or radio frequency sampling of the output of a power amplifier. Undersampling may be performed at a rate, which causes aliasing to occur in the undersampled frequency domain. Both undersampling and radio frequency sampling reduces the complexity of the digital pre-distortion system by removing any down mixing modules or anti-aliasing modules, while maintaining reasonable performance of the digital pre-distortion systems.

Abstract translation: 公开了用于发射机的各种数字预失真系统。 数字预失真系统包括观测路径，其执行功率放大器的输出的欠采样或射频采样。 可以以使得在欠采样频域中出现混叠的速率来执行不抽样。 欠采样和射频采样都可以通过去除任何下混频模块或抗混叠模块来降低数字预失真系统的复杂性，同时保持数字预失真系统的合理性能。

公开(公告)号：US20150014791A1

公开(公告)日：2015-01-15

申请号：US13939556

申请日：2013-07-11

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Edward John Coyne ,  Breandan Pol Og O hAnnaidh ,  Seamus P. Whiston ,  William Allan Lane ,  Donal P. McAuliffe

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/66477 ,  H01L29/66681 ,  H01L29/7824

Abstract: A semiconductor device having a first layer adjoining a semiconductor layer, and further comprising at least one field modification structure positioned such that, in use, a potential at the field modification structure causes an E-field vector at a region of an interface between the semiconductor and the first layer to be modified.

Abstract translation: 一种半导体器件，其具有与半导体层相邻的第一层，并且还包括至少一个场修改结构，其定位使得在使用中，场修改结构处的电位在半导体的界面区域处引起E场矢量 和要修改的第一层。

公开(公告)号：US08912936B1

公开(公告)日：2014-12-16

申请号：US13905251

申请日：2013-05-30

Applicant: Analog Devices Technology

Inventor： Trevor Clifford Caldwell ,  Richard E. Schreier ,  David Alldred ,  Wenhua W. Yang

IPC: H03M3/00

CPC classification number: H03M1/0673 ,  H03M1/361 ,  H03M1/74 ,  H03M3/30 ,  H03M3/338 ,  H03M3/464

Abstract: In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.

Abstract translation: 一方面，公开了一种电信号转换器。 示例性电信号转换器可以包括多个有序的转换器元件。 可以提供元素选择逻辑以伪随机选择指向开关矩阵的指针，其中开关矩阵根据逐步的“二进制二最大模式”来映射转换器元件。有利地，可以应用伪随机逐步的Δ-二最大模式 到一阶转换器和用于纠错的反馈转换器。

公开(公告)号：US20140347078A1

公开(公告)日：2014-11-27

申请号：US13899143

申请日：2013-05-21

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Song Qin

IPC: G01R19/00

CPC classification number: G01R19/0092 ,  H02M3/158 ,  H02M2001/0009

Abstract: Apparatus and methods for current sensing in switching regulators are disclosed. In certain implementations, a current sensing circuit senses current of a power stage of a power converter. The power converter can include first and second transistors. The current sensing circuit comprises a transistor that is a scaled version of one of the transistors of the power converter. A circuit of the current sensing circuit matches a drain-to-source voltage of the transistor of the current sensing circuit to the corresponding transistor of the power converter. A current mirror generates a current that mirrors the current flowing through the transistor of the current sensing circuit. A first resistor converts the mirrored current to a current sensed signal.

Abstract translation: 公开了用于开关调节器中的电流感测的装置和方法。 在某些实施方式中，电流感测电路感测功率转换器的功率级的电流。 功率转换器可以包括第一和第二晶体管。 电流感测电路包括晶体管，其是功率转换器的晶体管之一的缩放版本。 电流感测电路的电路将电流感测电路的晶体管的漏极 - 源极电压与功率转换器的相应晶体管相匹配。 电流镜产生反映流过电流感测电路的晶体管的电流的电流。 第一个电阻将镜像电流转换为电流检测信号。

公开(公告)号：US08887119B2

公开(公告)日：2014-11-11

申请号：US14028792

申请日：2013-09-17

Applicant: Analog Devices Technology

Inventor： Roger Feng ,  Junxiao Chen ,  Bin Shao

IPC: G06F17/50

CPC classification number: G06F17/5063 ,  G06F2217/78

Abstract: A method can reuse at least one pin in demultiplexing (demuxing) a voltage from a pin. The method can be used to set an accurate current limit threshold in a design for test (DFT) phase and, thus, to accurately set a trimming code of a current limiter. The method uses the property that a power MOSFET has almost a same conductive resistance at a large drain current. Thus, the current limit threshold can be set according to an accurate drain-to-source voltage Vds at a small current sink that is less than a maximum current that ATE is able to provide. An accurate voltage Vds can be measured through Kelvin sensing drain and source pins of the power MOSFET, which are connected to a current sense circuit.

Abstract translation: 一种方法可以在从引脚解复用（解调））电压时重用至少一个引脚。 该方法可用于在测试（DFT）相位的设计中设置精确的电流限制阈值，从而准确地设置限流器的修整代码。 该方法使用功率MOSFET在大漏极电流下具有几乎相同的导电电阻的性质。 因此，可以根据小于ATE能够提供的最大电流的小电流宿的准确的漏极 - 源极电压Vds来设置电流限制阈值。 可以通过连接到电流检测电路的功率MOSFET的开尔文感测漏极和源极引脚来测量精确的电压Vds。

公开(公告)号：US20140313066A1

公开(公告)日：2014-10-23

申请号：US14214341

申请日：2014-03-14

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Dennis A. Dempsey

IPC: H03M1/68

CPC classification number: H03M1/68 ,  H03M1/00 ,  H03M1/06 ,  H03M1/66 ,  H03M1/682 ,  H03M1/765

Abstract: A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. In one configuration, the DAC comprises a first and second switching network, the second switching network providing multiple switched paths which compensate for impedance effects of the second string and provides multiple state changes at the output node of the DAC.

Abstract translation: 描述多串DAC并且包括至少两个DAC级。 每个DAC级包括一串阻抗元件和一个交换网络。 在一种配置中，DAC包括第一和第二交换网络，第二交换网络提供多个交换路径，其补偿第二串的阻抗效应，并在DAC的输出节点处提供多个状态改变。

公开(公告)号：US08860500B2

公开(公告)日：2014-10-14

申请号：US13945978

申请日：2013-07-19

Applicant: Analog Devices Technology

Inventor： Linus Sheng ,  Christopher W. Mangelsdorf

IPC: G05F3/02

CPC classification number: G05F3/02 ,  H02M3/07 ,  H02M2003/075

Abstract: An apparatus for transferring charge has a first charge pump path with a plurality of stages having first capacitors, and a second charge pump path, also with a plurality of stage having second capacitors, in parallel with the first charge pump path. The first and second charge pump paths are coupled to share a common output node. The apparatus also has a timing circuit coupled with the first and second charge pump paths. Among other things, the timing circuit is configured to cause at least one of the first capacitors to periodically charge at least one of the second capacitors.

Abstract translation: 一种用于传送电荷的装置具有第一电荷泵路径，其具有多个阶段，该第一电荷泵路径具有第一电容器，第二电荷泵路径也具有与第一电荷泵路径并联的具有第二电容器的多个级。 第一和第二电荷泵路径被耦合以共享公共输出节点。 该装置还具有与第一和第二电荷泵路径耦合的定时电路。 其中，定时电路被配置为使得第一电容器中的至少一个周期性地对第二电容器中的至少一个充电。

公开(公告)号：US20140285369A1

公开(公告)日：2014-09-25

申请号：US14214405

申请日：2014-03-14

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Dennis A. Dempsey

IPC: H03M1/66

CPC classification number: H03M1/68 ,  H03M1/00 ,  H03M1/06 ,  H03M1/66 ,  H03M1/682 ,  H03M1/765

Abstract: A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. A control loop is provided to control the Ron of the switching network and provide code dependent control of switches in a DAC switching network.

Abstract translation: 描述多串DAC并且包括至少两个DAC级。 每个DAC级包括一串阻抗元件和一个交换网络。 提供控制回路来控制交换网络的Ron，并提供DAC交换网络中交换机的代码相关控制。

公开(公告)号：US20140266825A1

公开(公告)日：2014-09-18

申请号：US13920083

申请日：2013-06-18

Applicant: Analog Devices Technology

Inventor： Zhao Li ,  Shipra Bhal ,  Kevin Glenn Gard ,  David Alldred ,  Christopher Mayer ,  Trevor Clifford Caldwell ,  David J. McLaurin ,  Victor Kozlov

IPC: H03M1/10

CPC classification number: H03M3/384 ,  H03M1/00 ,  H03M1/1009 ,  H03M1/12 ,  H03M3/458

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract translation: 用于模数转换器（ADC）的校准系统，内部ADC接收模拟输入并将模拟输入转换为数字多位数据。 该校准系统还包括一个参考混洗电路，它洗牌内部ADC的比较器参考值。 此外，校准系统包括校准电路，校准内部ADC的比较器。 校准系统包括基于数字多位数据测量幅度的数字块。 此外，校准系统包括基于数字块的输出来控制校准电路的校准逻辑。