公开(公告)号：US06742335B2

公开(公告)日：2004-06-01

申请号：US10193257

申请日：2002-07-11

申请人： N. John Beck ,  Hoi Ching Wong ,  Kresimir Gebert

发明人： N. John Beck ,  Hoi Ching Wong ,  Kresimir Gebert

IPC分类号： F02B3344

CPC分类号： F02B37/16 ,  F01N3/021 ,  F01N3/043 ,  F02B29/0406 ,  F02B37/00 ,  F02M26/06 ,  F02M26/10 ,  F02M26/19 ,  F02M26/32 ,  F02M26/35 ,  F02M26/47 ,  Y02T10/144 ,  Y02T10/20

摘要： EGR mass fraction or a value indicative thereof can be calculated based on temperature measurements rather than mass flow and/or pressure measurements, hence negating the need for expensive and relatively unreliable measurement devices in an active EGR system for an internal combustion engine. The EGR system may be a low pressure EGR system configured to direct cooled, filtered EGR to the engine's air intake system using an effective, simple venturi and/or a continuously regenerated catalytic particulate trap. The resultant system can reduce NOx emissions in a diesel engine on the order of 50% and approximately 90% for CO, HC, and PM. NOx and other emissions can be reduced still further when the EGR system is combined with other pretreatment and/or after treatment devices. Many components of the low pressure EGR system are also usable in a passive EGR system.

摘要翻译： 可以基于温度测量而不是质量流量和/或压力测量来计算EGR质量分数或指示其的值，因此不需要用于内燃机的主动EGR系统中昂贵且相对不可靠的测量装置。 EGR系统可以是低压EGR系统，其被配置为使用有效的简单文丘里管和/或连续再生的催化颗粒捕集器将冷却过滤的EGR引导到发动机的进气系统。 所得到的系统可以将CO，HC和PM的柴油发动机中的NOx排放量减少约50％和约90％。 当EGR系统与其他预处理和/或后处理装置组合时，NOx和其它排放物可以进一步降低。 低压EGR系统的许多部件也可用于被动EGR系统。

公开(公告)号：US06558967B1

公开(公告)日：2003-05-06

申请号：US09775415

申请日：2001-01-31

申请人： Sau-Ching Wong

发明人： Sau-Ching Wong

IPC分类号： H01L2166

CPC分类号： G11C16/20 ,  G11C11/56 ,  G11C11/5621 ,  G11C2211/5641

摘要： A manufacturing method for a multiple-bit-per-cell memory tests memory arrays in the memory and separately sets the number of bits stored per cell in each memory array. Memory arrays that testing proves are accurate when writing, storing, and reading a larger number of bits per cell are set to store more bits per cell, and memory arrays that cannot accurately write, store, or read as many bits per cell are set to store fewer bits per cell. The setting of the numbers of bits per cell for the respective memory arrays can maximize the memory capacity when some arrays perform better than expected. When the memory arrays perform worse than expected, the setting of the numbers of bits per cell can salvage the memory device even if the memory cannot provide the expected memory capacity.

摘要翻译： 用于多比特单元存储器的制造方法测试存储器中的存储器阵列，并且分别设置每个存储器阵列中每个单元存储的位数。 当每个单元写入，存储和读取更多的位数时，测试证明的存储器阵列是准确的，以便存储每个单元更多的位，并且不能准确地写入，存储或读取每个单元的位数的存储器阵列被设置为 每个单元存储更少的位。 当某些阵列执行得比预期的更好时，各个存储器阵列的每个单元的位数的设置可以最大化存储器容量。 当存储器阵列执行得比预期差时，即使存储器不能提供预期的存储器容量，每个单元的位数的设置也可以对存储器件进行补救。

公开(公告)号：US06475816B1

公开(公告)日：2002-11-05

申请号：US09781435

申请日：2001-02-13

申请人： Concetta Riccobene ,  Nga-Ching Wong ,  Tim Thurgate

发明人： Concetta Riccobene ,  Nga-Ching Wong ,  Tim Thurgate

IPC分类号： H01L2166

CPC分类号： H01L22/14 ,  G01R31/27

摘要： A method is provided for accurately determining the junction depth of silicon-on-insulator (SOI) devices. Embodiments include determining the junction depth in an SOI device under inspection by measuring the threshold voltage of its “bottom transistor” formed by its source and drain regions together with its substrate acting as a gate. The threshold voltage of the bottom transistor of an SOI device varies with its junction depth in a predictable way. Thus, the junction depth of the inspected device is determined by comparing its bottom transistor threshold voltage with the bottom transistor threshold voltage of corresponding reference SOI devices of known junction depth to find a match. For example, simulated SOI devices with the same characteristics as the inspected device, whose junction depth and bottom transistor threshold voltages have been previously calculated, are used as a “reference library”. If the bottom transistor threshold voltage of the inspected device has about the same value as that of a particular one of the reference devices, then the inspected device has the junction depth of that particular reference device. Thus, junction depth of the inspected SOI device is accurately determined by a simple electrical measurement of threshold voltage.

摘要翻译： 提供了一种用于精确地确定绝缘体上硅（SOI）器件的结深度的方法。 实施例包括通过测量其源极和漏极区域形成的其“底部晶体管”及其衬底作为栅极的阈值电压来确定被检查的SOI器件中的结深度。 SOI器件的底部晶体管的阈值电压以其可预测的方式随其结深度而变化。 因此，通过将其底部晶体管阈值电压与已知结深度的相应参考SOI器件的底部晶体管阈值电压进行比较来确定被检查器件的结深度以找到匹配。 例如，具有与被预先计算的结深度和底部晶体管阈值电压的被检查器件相同特性的模拟SOI器件被用作“参考库”。 如果被检查装置的底部晶体管阈值电压具有与特定参考装置的底部晶体管阈值电压相同的值，则所检查的装置具有该特定参考装置的结深度。 因此，通过阈值电压的简单电测量精确地确定被检查的SOI器件的结深度。

公开(公告)号：US06317349B1

公开(公告)日：2001-11-13

申请号：US09293134

申请日：1999-04-16

申请人： Sau-ching Wong

发明人： Sau-ching Wong

IPC分类号： G11C1500

CPC分类号： G11C15/046

摘要： A content addressable memory (CAM) includes non-volatile CAM cells that are in an array similar to a conventional Flash memory array. In the CAM, each word line connects to control gates of Flash memory cells in a row, each bit line connects to drains of Flash memory cells in a column, and each match line is a source line coupled to sources of Flash memory cells in a row. A 2-T CAM cell includes a pair of non-volatile devices coupled to the same word line and match line. Each non-volatile device can be a floating-gate transistor, a Flash memory cell, or a shared-floating-gate (SFG) device. An erase of a CAM word applies erase voltages to the word and match lines associated with the word. The erase does not depend on the bit line voltages. Accordingly, the CAM array can simultaneously perform a search and an erase. With SFG devices, the CAM array can also simultaneously perform a search and a program operation. A CAM buffer stores words to be written in the array and can also conducts a search during an erase so that the CAM can perform back-to-back write and search operations without waiting for completion of an erase operation. A dual CAM cell includes a combination of two CAM elements, each CAM cells being, for example, a known or new 2-T CAM cell. The first element stores a data bit of a CAM word. A second element is programmed to either represent the data bit or a “don't care” state. A search without masking uses the first element in each dual CAM cell, and a search with masking uses some or all of the second elements depending on a mask selection register. To change masking for a particular CAM word, the first element is read, and the second element is reprogrammed according to the value read and the desired masking.

摘要翻译： 内容可寻址存储器（CAM）包括与常规闪存阵列类似的阵列的非易失性CAM单元。 在CAM中，每个字线连接到一行中的闪存单元的控制栅极，每个位线连接到列中的闪存单元的排水口，并且每个匹配线是耦合到闪存单元的源的源极线 行。 2-T CAM单元包括耦合到相同字线和匹配线的一对非易失性器件。 每个非易失性器件可以是浮栅晶体管，闪存单元或共享浮栅（SFG）器件。 CAM字的擦除将对该字应用擦除电压并匹配与该字相关联的线。 擦除不依赖于位线电压。 因此，CAM阵列可以同时执行搜索和擦除。 使用SFG设备，CAM阵列还可以同时执行搜索和程序操作。 CAM缓冲器存储要写入阵列的字，并且还可以在擦除期间进行搜索，使得CAM可以执行背靠背写入和搜索操作而不等待擦除操作的完成。 双CAM单元包括两个CAM元件的组合，每个CAM单元例如是已知的或新的2-T CAM单元。 第一个元素存储CAM字的数据位。 第二个元素被编程为表示数据位或“无关”状态。 无掩蔽的搜索使用每个双CAM单元中的第一元素，并且具有掩蔽的搜索根据掩码选择寄存器使用部分或全部第二元素。 要更改特定CAM字的掩码，读取第一个元素，并根据读取的值和所需的掩码重新编程第二个元素。

公开(公告)号：US06259627B1

公开(公告)日：2001-07-10

申请号：US09493026

申请日：2000-01-27

申请人： Sau Ching Wong

发明人： Sau Ching Wong

IPC分类号： G11C1606

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

摘要： A read operation for a multi-level or a multi-bit-per-cell non-volatile memory biases a selected row line cell at a fixed voltage that is above the maximum possible threshold voltage representing data and changes the column line load for a selected column line. The column line load that corresponds to the trip-point of a sense amplifier indicates the data stored in the memory cell coupled to the selected row and column lines. A corresponding write process uses the same fixed row line voltage for both program and verify cycles. The programming voltage can be the same as the row line voltage for the read operation or can depend on the data value being written. To better control programming, the duration of the program cycles and/or the load on the drain or source of the selected memory cell during a program cycle varies with time and depends on the value being written. One memory in accordance with the invention includes variable column line loads for use during read and write operations. The variable loads can select the programming current for the write operation or the bias for the read operation according to a data value and/or a count. A counter generating the count for the variable loads can be used during a read operation to change the column line bias until the trip-point of a sense amplifier is found and during a write operation to reduce programming current when the threshold voltage of the selected memory cell nears the target threshold voltage level.

摘要翻译： 用于多电平或多比特单元非易失性存储器的读取操作以高于表示数据的最大可能阈值电压的固定电压来偏置所选行行单元，并且改变所选择的列线负载 列线。 对应于读出放大器的跳变点的列线负载指示存储在与所选行和列线相连的存储单元中的数据。 相应的写入过程对于程序和验证周期都使用相同的固定行线电压。 编程电压可以与读取操作的行线电压相同，也可以取决于正在写入的数据值。 为了更好地控制编程，程序循环的持续时间和/或所选存储单元的漏极或源极上的负载在编程周期内随时间而变化，并且取决于所写入的值。 根据本发明的一个存储器包括用于在读取和写入操作期间使用的可变列线负载。 可变负载可以根据数据值和/或计数来选择用于写入操作的编程电流或用于读取操作的偏置。 可以在读取操作期间使用产生可变负载的计数的计数器来改变列线偏压，直到发现读出放大器的跳变点，并且在写操作期间，当所选择的存储器的阈值电压 电池接近目标阈值电压电平。

公开(公告)号：US06134141A

公开(公告)日：2000-10-17

申请号：US224656

申请日：1998-12-31

申请人： Sau-Ching Wong

发明人： Sau-Ching Wong

IPC分类号： G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C27/00 ,  G11C11/34

CPC分类号： G11C7/1039 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C27/005 ,  G11C2211/5621 ,  G11C2211/5645

摘要： A write process and circuit for a non-volatile memory such as a multi-bit-per-cell Flash memory has multiple local memory arrays and a global bias circuit that charges row lines in the arrays for programming operations. A programming operation in an array includes a charging period during which the global bias circuit charges a selected row line to a voltage corresponding to a value to be written in a memory cell and a sequence of program cycles and verify cycles during which the selected row line is isolated to preserve the charge from the bias circuit. A global control circuit can use a capacitive coupling to the charged row line to raise and lower the row line voltage. In one embodiment, the row line voltage rises to a programming voltage to change the threshold voltage of the selected cell during program cycles and falls to a verify voltage during verify cycles to sense whether the selected cell has a target threshold voltage. Alternatively, the row line voltage remains constant as charged by the bias circuit if a maximum current for biasing a column line connected to a sense amplifier causes the programming voltage to be equal to the trip point of the sense amplifier when the memory cell has the target threshold voltage.

摘要翻译： 用于非易失性存储器的写入处理和电路，例如每位多比特闪存存储器具有多个本地存储器阵列和用于对阵列中的行线进行编程操作的全局偏置电路。 阵列中的编程操作包括充电周期，在该充电周期期间，全局偏置电路将所选择的行线充电到与要写入存储器单元的值相对应的电压以及编程周期和验证周期的序列，在该周期期间，所选择的行线 被隔离以保持来自偏置电路的电荷。 全局控制电路可以使用与充电行线的电容耦合来升高和降低行线电压。 在一个实施例中，行线电压上升到编程电压以在编程周期期间改变所选择的单元的阈值电压，并且在验证周期期间下降到验证电压以检测所选择的单元是否具有目标阈值电压。 或者，如果用于偏置连接到读出放大器的列线的最大电流使得当存储器单元具有目标时编程电压等于读出放大器的跳变点，则行线电压保持恒定，由偏置电路充电 阈值电压。

公开(公告)号：US5853124A

公开(公告)日：1998-12-29

申请号：US851476

申请日：1997-05-05

申请人： Niels John Beck ,  William P. Johnson ,  Kresimir Gebert ,  Hoi Ching Wong

发明人： Niels John Beck ,  William P. Johnson ,  Kresimir Gebert ,  Hoi Ching Wong

IPC分类号： F02M61/06 ,  F02M61/18 ,  F02M3/08

CPC分类号： F02M61/06 ,  F02M61/18

摘要： A pintle nozzle, preferably an unthrottled pintle nozzle, is provided in which a negative interference angle is formed between the conical tip of the nozzle needle and the mating conical valve seat so that the needle seat is located at the bottom of the valve seat rather than at the top. The resulting nozzle lacks any velocity drop downstream of the needle seat, even at very low needle lifts, so that virtually all of the energy used to pressurize the fuel is converted to kinetic energy. Spray dispersion and penetration at low needle lifts therefore are significantly enhanced. Fuel flow through the converging-diameter discharge passage located between the conical needle tip and conical needle seat also self-centers the nozzle needle at low lifts, thereby helping to assure a symmetric spray and to further enhance spray characteristics. These and other advantages render the nozzle particularly useful for applications which require very small injection quantities such as the injection of fuel into small two-stroke gasoline engines or into pilot-ignited gas-fueled engines.

摘要翻译： 提供了一种枢轴喷嘴，优选为无节流的枢轴喷嘴，其中在喷嘴针的锥形尖端和配合锥形阀座之间形成负干涉角，使得针座位于阀座的底部，而不是 在顶部。 所得到的喷嘴在针座的下游没有任何速度下降，即使在非常低的针升降机上，因此几乎所有用于加压燃料的能量都被转换成动能。 因此，在低针电梯处的喷雾分散和渗透显着增强。 通过位于锥形针尖和圆锥形针座之间的会聚直径排出通道的燃料流动也使喷嘴针在低升程中自中心，从而有助于确保对称喷雾并进一步增强喷雾特性。 这些和其它优点使得喷嘴对于需要非常小的喷射量的应用特别有用，例如将燃料喷射到小型二冲程汽油发动机或引燃点燃的燃气发动机中。

公开(公告)号：US4864161A

公开(公告)日：1989-09-05

申请号：US190530

申请日：1988-05-05

申请人： Kevin A. Norman ,  Hock-Chuen So ,  Kerry S. Veenstra ,  Sau-Ching Wong

发明人： Kevin A. Norman ,  Hock-Chuen So ,  Kerry S. Veenstra ,  Sau-Ching Wong

IPC分类号： H03K3/037

CPC分类号： H03K3/037

摘要： A flip-flop-type circuit capable of operating either as a conventional D flip-flop or as a device which merely passes through the data applied to it (so-called "flow-through mode"). In the flow-through mode, the circuit has the additional capability of being able to latch in the data flowing through it at any time. Thus the circuit can also operate as a level-sensitive latch.

公开(公告)号：US4774421A

公开(公告)日：1988-09-27

申请号：US907075

申请日：1986-09-12

申请人： Robert F. Hartmann ,  Sau-Ching Wong ,  Yiu-Fai Chan ,  Jung-Hsing Ou

发明人： Robert F. Hartmann ,  Sau-Ching Wong ,  Yiu-Fai Chan ,  Jung-Hsing Ou

IPC分类号： H03K5/02 ,  H03K17/693 ,  H03K19/094 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K17/693 ,  H03K19/09425 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17712 ,  H03K5/023

摘要： A programmable logic array device basically comprising a programmable AND gate array (FIGS. 5, 11) having addressable rows (40-45) and columns (32-38) or memory cells (30, 31) which can be individually programmed to represent logic data; an input signal receiving circuit (FIG. 9) for developing a corresponding buffered input signal; a first row driver (FIG. 10) responsive to the buffered signal and operative to cause a particular row of memory cells in an AND array (FIG. 11) to output corresponding logical product of AND-input signals, OR/NOR sensing circuitry (FIG. 12) for sensing the AND array product signals and for developing therefrom corresponding logical OR sum signals; circuit means output terminal circuitry; output switching circuitry (FIG. 14) responsive to a control signal and operative to couple either the circuit means output signal or a registered (FIG. 13) output to a device input or output terminal (FIG. 16); feedback switching circuitry similarly responsive to a control signal and operative to couple either the circuit means output signal, registered output signal, or feedback signal to a row driver; and Reprogrammable Architecture control circuitry (FIG. 24) to provide control signals to said switching circuitry. The device has the advantages of increased density of useable logic functions, and decreased power consumption.

摘要翻译： 可编程逻辑阵列器件基本上包括具有可寻址行（40-45）和列（32-38）或存储器单元（30,31）的可编程与门阵列（图5,11），其可以被单独编程以表示逻辑 数据; 输入信号接收电路（图9），用于开发相应的缓冲输入信号; 第一行驱动器（图10），响应于缓冲的信号并且可操作以使AND阵列（图11）中的特定行的存储器单元输出对应的AND输入信号的逻辑积OR / NOR感测电路（ 图12），用于感测AND阵列产品信号并用于从其产生相应的逻辑或和信号; 电路表示输出端子电路; 输出切换电路（图14），响应于控制信号并且可操作地将电路装置输出信号或注册的（图13）输出耦合到设备输入或输出端子（图16）; 反馈切换电路类似地响应于控制信号并且可操作地将电路装置的输出信号，已注册的输出信号或反馈信号耦合到行驱动器; 和可重编程架构控制电路（图24），以向所述开关电路提供控制信号。 该器件具有可用逻辑功能密度增加，功耗降低的优点。