公开(公告)号：US20080296664A1

公开(公告)日：2008-12-04

申请号：US12185751

申请日：2008-08-04

Applicant: Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

IPC: H01L29/792 ,  H01L21/28

CPC classification number: H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

公开(公告)号：US20080293255A1

公开(公告)日：2008-11-27

申请号：US12124855

申请日：2008-05-21

Applicant: Krishnaswamy Ramkumar

Inventor： Krishnaswamy Ramkumar

IPC: H01L21/31

CPC classification number: H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/4234 ,  H01L29/66833

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed Thereon. A portion of the charge-trapping layer is then oxidized to form a blocking Dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.

Abstract translation: 描述了制造非易失性电荷陷阱存储器件的方法。 该方法包括提供其上设置有电荷捕获层的衬底。 然后通过将电荷捕获层暴露于自由基氧化过程，电荷俘获层的一部分被氧化以形成电荷俘获层上方的阻挡介电层。

公开(公告)号：US20080293254A1

公开(公告)日：2008-11-27

申请号：US11904513

申请日：2007-09-26

Applicant: Krishnaswamy Ramkumar ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Sagy Levy

IPC: H01L21/314

CPC classification number: H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/4234 ,  H01L29/66833 ,  Y10S438/954

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.

Abstract translation: 描述了制造非易失性电荷陷阱存储器件的方法。 该方法包括首先在单晶片簇工具的第一处理室中的衬底上形成隧道电介质层。 然后在单晶片簇工具的第二处理室中的隧道介电层上形成电荷捕获层。 然后在单晶片簇工具的第二或第三处理室中的电荷俘获层上形成顶部电介质层。

公开(公告)号：US20080293207A1

公开(公告)日：2008-11-27

申请号：US12125864

申请日：2008-05-22

Applicant: William W.C. Koutny, JR. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

Inventor： William W.C. Koutny, JR. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract translation: 一种半导体结构及其形成方法。 半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。 可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。 可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。 在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。 可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

公开(公告)号：US20080093680A1

公开(公告)日：2008-04-24

申请号：US11961750

申请日：2007-12-20

Applicant: Krishnaswamy Ramkumar ,  Sundar Narayanan

Inventor： Krishnaswamy Ramkumar ,  Sundar Narayanan

IPC: H01L29/78 ,  H01L21/31

CPC classification number: H01L21/022 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02337 ,  H01L21/28044 ,  H01L21/3144 ,  H01L29/4941 ,  H01L29/78

Abstract: A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.

Abstract translation: 制造半导体结构的方法包括在衬底上形成氧化物层; 在氧化物层上形成氮化硅层; 在NO中退火层; 并在氨中退火层。 氧化物层和氮化硅层的等效氧化物厚度在一起为至多25埃。

公开(公告)号：US07256083B1

公开(公告)日：2007-08-14

申请号：US10185646

申请日：2002-06-28

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar

IPC: H01L21/8238

CPC classification number: H01L21/28247 ,  H01L21/28061 ,  H01L29/4941

Abstract: A method of making a semiconductor structure includes depositing a nitride layer, on a metallic layer, by PECVD. The metallic layer is on a gate layer containing silicon, and the gate layer is on a semiconductor substrate.

Abstract translation: 制造半导体结构的方法包括通过PECVD在金属层上沉积氮化物层。 金属层位于含硅的栅极层上，栅极层位于半导体衬底上。

公开(公告)号：US07189652B1

公开(公告)日：2007-03-13

申请号：US10313048

申请日：2002-12-06

Applicant: Alain Blosse ,  Sundar Narayanan ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Sundar Narayanan ,  Krishnaswamy Ramkumar

IPC: H01L21/302

CPC classification number: H01L21/28247 ,  H01L21/28061

Abstract: A method of forming a semiconductor structure comprises oxidizing a stack, to form sidewall oxide in contact with sides of the stack. The stack is on a semiconductor substrate, the stack includes a gate layer, comprising silicon; a metallic layer, on the gate layer; and an etch-stop layer, on the metallic layer. The sidewall oxide in contact with the metallic layer is thinner than the sidewall oxide in contact with the gate layer.

Abstract translation: 形成半导体结构的方法包括氧化堆叠，以形成与堆叠的侧面接触的侧壁氧化物。 堆叠在半导体衬底上，堆叠包括包含硅的栅极层; 栅极层上的金属层; 和金属层上的蚀刻停止层。 与金属层接触的侧壁氧化物比与栅极层接触的侧壁氧化物薄。

公开(公告)号：US07094707B1

公开(公告)日：2006-08-22

申请号：US10142963

申请日：2002-05-13

Applicant: Krishnaswamy Ramkumar ,  Sundar Narayanan

Inventor： Krishnaswamy Ramkumar ,  Sundar Narayanan

IPC: H01L23/58

CPC classification number: H01L21/28202 ,  H01L21/28035 ,  H01L29/518

Abstract: A method of nitriding a gate oxide layer by annealing a preformed oxide layer with nitric oxide (NO) gas in a hot wall, single wafer furnace is provided. The nitridation process can be carried out rapidly (i.e., at nitridation times of 30 seconds to 2 minutes) while providing acceptable levels of nitridation (i.e., up to 6 at. %) and desirable nitrogen/depth profiles. The nitrided gate oxide layer can optionally be reoxidized in a second oxidation step after the nitridation step. A gate electrode layer (e.g., boron doped polysilicon) can then be deposited on top of the nitrided gate oxide layer or on top of the reoxidized and nitrided gate oxide layer.

Abstract translation: 提供了一种通过在热壁中的一氧化氮（NO）气体退火预形成的氧化物层来对栅极氧化物层进行氮化的方法。 氮化处理可以快速进行（即，在30秒至2分钟的氮化时间），同时提供可接受的氮化水平（即高达6原子％）和所需的氮/深度分布。 氮化栅氧化层可以在氮化步骤后的第二氧化步骤中任选地再氧化。 然后可以在氮化栅极氧化物层的顶部上或在再氧化和氮化的栅极氧化物层的顶部上沉积栅极电极层（例如，硼掺杂的多晶硅）。

公开(公告)号：US07026235B1

公开(公告)日：2006-04-11

申请号：US10072164

申请日：2002-02-07

Applicant: Mira Ben-Tzur ,  Krishnaswamy Ramkumar

Inventor： Mira Ben-Tzur ,  Krishnaswamy Ramkumar

IPC: H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/76807 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, an interconnect line on one level of an integrated circuit is electrically coupled to another interconnect line on another level. The two layers of interconnects may be coupled together using a via. To reduce capacitance between the interconnect lines, an air core is formed between them. The air core may be formed by using a chemistry that includes a noble gas fluoride to etch a sacrificial layer between the interconnect layers.

Abstract translation: 在一个实施例中，集成电路的一个电平上的互连线电连接到另一个电平上的另一个互连线。 两层互连可以使用通孔耦合在一起。 为了减小互连线之间的电容，在它们之间形成空芯。 空芯可以通过使用包含惰性气体氟化物的化学物质来形成，以蚀刻互连层之间的牺牲层。

公开(公告)号：US06969684B1

公开(公告)日：2005-11-29

申请号：US09846119

申请日：2001-04-30

Applicant: Yitzhak Gilboa ,  William W. C. Koutny, Jr. ,  Steven Hedayati ,  Krishnaswamy Ramkumar

Inventor： Yitzhak Gilboa ,  William W. C. Koutny, Jr. ,  Steven Hedayati ,  Krishnaswamy Ramkumar

IPC: H01L21/302 ,  H01L21/3105 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/31055

Abstract: A method is provided for eliminating a polish stop layer from a polishing process. In particular, a method is provided which may include polishing an upper layer of a semiconductor topography to form an upper surface at an elevation above an underlying layer, wherein the upper surface does not include a polish stop material. Preferably, the upper surface of the topography formed by polishing is spaced sufficiently above the underlying layer to avoid polishing the underlying layer. The entirety of the upper surface may be simultaneously etched to expose the underlying layer. In an embodiment, the underlying layer may comprise a lateral variation in polish characteristics. The method may include using fixed abrasive polishing of a dielectric layer for reducing a required thickness of an additional layer underlying the dielectric layer. Such a method may be useful when exposing an underlying layer is desirable by techniques other than polishing.

Abstract translation: 提供了一种从抛光过程中消除抛光停止层的方法。 特别地，提供了一种方法，其可以包括抛光半导体形貌的上层以形成在下层之上的高度上的上表面，其中上表面不包括抛光停止材料。 优选地，通过抛光形成的形貌的上表面被充分地间隔在下面的层上，以避免抛光下面的层。 可以同时蚀刻整个上表面以暴露下层。 在一个实施例中，下层可以包括抛光特性的横向变化。 该方法可以包括使用介电层的固定研磨抛光来减少介电层下面的附加层的所需厚度。 当通过除了抛光之外的技术来期望暴露下层时，这种方法可能是有用的。