公开(公告)号：US07112539B2

公开(公告)日：2006-09-26

申请号：US10999608

申请日：2004-11-29

Applicant: Jongho Lee ,  Nae-In Lee

Inventor： Jongho Lee ,  Nae-In Lee

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises one or more ordered pairs of first and second layers. With the present invention, the dielectric constant of the high-k dielectric layer can be optimized while improving interface characteristics. With a higher crystallization temperature realized by forming the multi-layer structure, each of whose layers is not more than the critical thickness, leakage current can be reduced, thereby improving device performance.

公开(公告)号：US07092298B2

公开(公告)日：2006-08-15

申请号：US10916716

申请日：2004-08-12

Applicant: Ki-Chul Kim ,  Nae-In Lee ,  Geum-Jong Bae

Inventor： Ki-Chul Kim ,  Nae-In Lee ,  Geum-Jong Bae

IPC: G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0416 ,  G11C16/0425 ,  G11C16/0466 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/66833

Abstract: Methods of erasing a non-volatile memory device having discrete charge trap sites between a semiconductor substrate and a gate include applying a negative voltage to a gate at least partially spaced apart from a semiconductor substrate by a charge storage layer providing discrete charge trap sites. A first positive voltage is applied to a source formed in the semiconductor substrate adjacent to one sidewall of the gate. A second positive voltage, which is equal to or less than the first positive voltage, is applied to a drain formed in the semiconductor substrate adjacent to the gate and located opposite the source.

Abstract translation: 擦除在半导体衬底和栅极之间具有离散电荷陷阱位置的非易失性存储器件的方法包括通过提供离散电荷陷阱位置的电荷存储层将至少部分地与半导体衬底间隔开的栅极施加负电压。 第一正电压施加到与栅极的一个侧壁相邻的半导体衬底中形成的源。 将等于或小于第一正电压的第二正电压施加到与栅极相邻并位于与源相对的半导体衬底中形成的漏极。

公开(公告)号：US07060563B2

公开(公告)日：2006-06-13

申请号：US10953553

申请日：2004-09-30

Applicant: Geum-Jong Bae ,  Nae-In Lee ,  Sang Su Kim ,  Ki Chul Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

Inventor： Geum-Jong Bae ,  Nae-In Lee ,  Sang Su Kim ,  Ki Chul Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

IPC: H01L21/8247

CPC classification number: H01L29/792 ,  H01L29/7923 ,  Y10S438/954

Abstract: A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the first gate layer and on the gate insulator. The first and second gate layers are electrically connected together. Together, the ONO structure and first and second gate layers define at least a 1-bit local SONOS structure. A corresponding method of manufacture includes: providing a substrate; forming an ONO structure on the substrate; forming a first gate layer on and aligned with the ONO structure; forming a gate insulator on the substrate aside the ONO structure; forming a second gate layer on the first gate layer and on the gate insulator; and electrically connecting the first and second gate layers.

Abstract translation: 具有两件式门和自对准ONO结构的本地SONOS结构包括：衬底; 基底上的ONO结构; 在ONO结构上并与ONO结构对准的第一栅极层; 衬底上的栅极绝缘体旁边的ONO结构; 以及在第一栅极层上和栅极绝缘体上的第二栅极层。 第一和第二栅极层电连接在一起。 ONO结构和第一和第二栅极层一起定义至少1位本地SONOS结构。 相应的制造方法包括：提供衬底; 在基板上形成ONO结构; 在ONO结构上形成第一栅极层并与其结合; 在衬底上形成栅极绝缘体，除了ONO结构; 在第一栅极层和栅极绝缘体上形成第二栅极层; 并且电连接第一和第二栅极层。

公开(公告)号：US20060054965A1

公开(公告)日：2006-03-16

申请号：US11269624

申请日：2005-11-09

Applicant: Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

Inventor： Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

IPC: H01L29/788

CPC classification number: H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.

公开(公告)号：US20050151184A1

公开(公告)日：2005-07-14

申请号：US11027256

申请日：2004-12-30

Applicant: Jong-Ho Lee ,  Nae-In Lee

Inventor： Jong-Ho Lee ,  Nae-In Lee

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/788 ,  H01L29/94 ,  H01L21/336 ,  H01L29/76 ,  H01L31/062

CPC classification number: H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract translation: 半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。 高k电介质层包括金属合金氧化物。

公开(公告)号：US06693032B2

公开(公告)日：2004-02-17

申请号：US09892362

申请日：2001-06-27

Applicant: Bong-young Yoo ,  Dae-hong Ko ,  Nae-in Lee ,  Young-wook Park

Inventor： Bong-young Yoo ,  Dae-hong Ko ,  Nae-in Lee ,  Young-wook Park

IPC: H01L213205

CPC classification number: H01L23/485 ,  H01L21/28061 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/53271 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/4983 ,  H01L2924/0002 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908 ,  H01L2924/00

Abstract: A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.

Abstract translation: 提供了采用上下导电层之间的层间接触结构的半导体器件以及采用该结构制造半导体器件的方法。 下导电层包括堆叠在一起的第一导电层和第一硅化物层。 上导电层包括掺杂有杂质的第二导电层和堆叠在一起的第二硅化物层。 在层间接触结构中，第一和第二导电层彼此直接接触。 这降低了两个导电层之间的接触电阻并改善了器件的电性能。

公开(公告)号：US06486039B2

公开(公告)日：2002-11-26

申请号：US09933039

申请日：2001-08-21

Applicant: Jae-yoon Yoo ,  Jeong-soo Lee ,  Nae-in Lee

Inventor： Jae-yoon Yoo ,  Jeong-soo Lee ,  Nae-in Lee

IPC: H01L21302

CPC classification number: H01L21/76229 ,  H01L21/76237

Abstract: A method of fabricating a trench isolation structure in a high-density semiconductor device that provides an isolation characteristic that is independent of the properties of adjacent MOS transistor devices, wherein a first trench in a first isolation area and a second trench implanted are formed on a semiconductor substrate, a nitrogen (N)-rich silicon layer is formed on the sidewall in a second isolation area, a subsequent oxidation process may be employed to fabricate oxide layers, each having a different thickness, on the sidewall surfaces of the first and second trenches. When the first and second oxide-layered trenches are filled with a stress relief liner and a dielectric material, the different thicknesses of the oxides prevent leakage currents from flowing to an adjacent semiconductor device, regardless of the doping properties of each device.

公开(公告)号：US06461984B1

公开(公告)日：2002-10-08

申请号：US09535156

申请日：2000-03-24

Applicant: Chui-Hi Han ,  Nae-In Lee ,  Sung-Hoi Hur ,  Jin-Woo Lee

Inventor： Chui-Hi Han ,  Nae-In Lee ,  Sung-Hoi Hur ,  Jin-Woo Lee

IPC: H01L2131

CPC classification number: H01L29/6675 ,  H01L21/28273 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/78609 ,  H01L29/7883

Abstract: The present invention provides a highly reliable polycrystal silicon thin film transistor with N2O plasma oxide having an excellent leakage current characteristics comparable to the thermal oxide film formed on the crystalline silicon. Also, the present invention provides a method of fabricating EEPROM or flash memory using N2O plasma oxide as a tunnel oxide, and N2O plasma oxide film as an interpoly dielectric between the floating gate and the control gate.

Abstract translation: 本发明提供一种具有N2O等离子体氧化物的高度可靠的多晶硅薄膜晶体管，其具有与形成在结晶硅上的热氧化膜相当的优异的漏电流特性。另外，本发明提供一种使用N2O制造EEPROM或闪存的方法 等离子体氧化物作为隧道氧化物，N2O等离子体氧化膜作为浮置栅极和控制栅极之间的多晶硅电介质。