Abstract:
The invention relates to a circuit (100) for use with a loudspeaker (104) having a first differential input terminal (t1) and a second differential input terminal (t2), the circuit (100) comprising: a differential power amplifier (103) having a first differential output terminal (t3) operatively connected to the first differential input terminal (t1) of the loudspeaker (104) and a second differential output terminal (t4) operatively connected to the second differential input terminal (t2) of the loudspeaker (104);—a first resistor (RS1) disposed between the first differential output terminal (t3) of the differential power amplifier (103) and the first differential input terminal (t1) of the loudspeaker (104); a second resistor (RS2) disposed between the second differential output terminal (t4) of the differential power amplifier (103) and the second differential input terminal (t2) of the loudspeaker (104). The circuit (100) further comprises: a first resistive module (RR1, RR2) arranged to generate on a respective output terminal (t5) a first control voltage (VIN), the first resistive module (RR1, RR2) having a first input terminal (t6) connected to the first differential output terminal (t3) of the power amplifier (103) and a second input terminal (t7) connected to the second differential input terminal (t2) of the loudspeaker (104), a second resistive module (RR3, RR4) arranged to generate on a respective output terminal (t8) a second control voltage (VIP), the second resistive module (RR3, RR4) having a first input terminal (t9) connected to the second differential output terminal (t4) of the power amplifier (103) and a second input terminal (t10) connected to the first differential input terminal (t1) of the loudspeaker (104). The loudspeaker circuit (100) being arranged to control the differential power amplifier (103) on the basis of the first control voltage (VIN) and the second control voltage (VIP).
Abstract:
A switching circuit (100, 200) for switching a voltage at an output node (120), comprises a first switch element (T1) coupled between a first supply node (110) and the output node (120), the first supply node (110) being at a first supply voltage (VDD), and a second switch element (T2) coupled between a second supply node (130) and the output node (120), the second supply node (130) being at a second supply voltage (Vss)- A switch controller (140) is arranged to, dependent on an input signal (VIN), switch the switching circuit (100, 200) between a first state, in which the first switch element (T1) is in a conducting state and the second switch element (T2) is in a non-conducting state, and a second state, in which the first switch element (T1) is in a non-conducting state and the second switch element (T2) is in a conducting state, through an intermediate state in which both the first switch element (T1) and the second switch element (T2) are in the non-conducting state.
Abstract:
Some embodiments of the invention concern a method of communication in a cellular network between a base station and a user equipment, comprising a step (S2) of providing, from base station to user equipment, a new allowed maximum transmitting power lower than former allowed maximum transmitting power because of traffic load increase within base station cell, wherein, if user equipment sends later on a message, to base station, with a transmitting power exceeding said new maximum, base station may decide not to reject (S10, S15) user equipment message depending on at least one condition.
Abstract:
The invention proposes a built-in self-testing method of a near field communication device including several functions, comprising testing a first internal communication link between a first function and a second function, by sending, on said first internal communication link, a first command from said first function used as a transmitter to said second function used as a receiver, and by checking said first command has been correctly executed by said second function.
Abstract:
A receiver receives a desired radio sub-channel transmitted with an unwanted radio sub-channel by producing signal branches from a received radio signal by treating orthogonal components of the received signal separately and also by using one or both of oversampling and multiple receive antennas. Channel estimates for both the desired and unwanted radio sub-channels are produced for signal branches. The unwanted radio sub-channel bits are estimated from a non-stacked form of the received radio signal. The channel estimates and the estimate of the unwanted radio sub-channel bits are used to reconstruct unwanted radio sub-channel components separately for signal branches. Desired radio sub-channel signal branches are produced by subtracting a corresponding one of the reconstructed unwanted radio sub-channel components from signal branches. A non-stacked desired signal is produced by combining the desired radio sub-channel signal branches. The non-stacked desired signal is processed to receive the desired radio sub-channel.
Abstract:
An apparatus (300) for use in a telecommunications system is disclosed. The apparatus (300) comprises a memory (340) and a controller (310). The apparatus (300) is configured to receive a radio frequency signal (150), determine an operating parameter and adapt a first filter function according to at least said operating parameter. The apparatus (300) is further configured to generate a filtered signal (720, 820, 730, 830) by applying said first filter function to a signal associated with the received radio frequency signal and provide said filtered signal (720, 82, 70, 830) for radio resource management.
Abstract:
An oscillator (200, 300, 350) comprises a tank circuit (100), a first transistor (M1c) and a second transistor (M1r), and the second transistor (M1r) occupies an area of silicon that is smaller than an area of silicon occupied by the first transistor (M1c). A switching apparatus (Sw1 . . . Sw14) selects either one of a first oscillator topology and a second oscillator topology, where in the first oscillator topology, the tank circuit (100) is coupled to the first transistor (M1c) in a first feedback configuration to provide feedback around the first transistor (M1c), and in the second oscillator topology, the tank circuit (100) is coupled to the second transistor (M1r) in a second feedback configuration that is different to the first feedback configuration to provide feedback around the second transistor (M1r).
Abstract:
Method of data processing for selectively activating, at a mobile station (1, 2), a mode of communication related to VAMOS-2 technology, the method comprising the steps of:—receiving a first signal of a first subchannel (C1), the first signal containing a first training sequence (mwant), and receiving a second signal of a second subchannel (C2), the second signal containing a second training sequence (mosc), the second signal being orthogonally multiplexed with respect to the first signal,—using the first training sequence and the second training sequence to:—determine a value of a parameter (α) defining a ratio between the first subchannel power and the second subchannel power, and—determine a signal to noise ratio estimation, and—determining, using the parameter value and the signal to noise estimation, whether the said mode of communication has to be activated.
Abstract:
A Power amplifier circuit based on a cascode structure and to be powered by a power source voltage, e.g. a battery, said circuit comprising—a first transistor having a grid, source and drain terminal; said first transistor being connected in a common source mode;—a second grid source transistor having grid, source and drain terminal, said second transistor being connected in common grid mode;—a biasing circuit for biasing said first transistor and said second transistor. The PA is characterized in that it includes a circuit for sensing the value of the power source voltage and for generating at least a first and a second biasing voltage for the grid of said second transistor in accordance with the power source voltage sensed, said first biasing voltage providing substantially equal protection to said first and second transistors when said power source voltage is sensed to be at a high voltage and said second biasing voltage providing more voltage to said first transistor when said power source voltage is sensed to be at a low voltage.
Abstract:
A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator, a digital integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The feedback analog signal is injected via the feedback path and the computation block directly at the input terminal of the quantizer. The converter allows reduction of the complexity of the quantizer.