公开(公告)号：US09455247B2

公开(公告)日：2016-09-27

申请号：US15087622

申请日：2016-03-31

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Jean Jimenez

IPC: H01L29/747 ,  H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0255 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/0292 ,  H01L29/7416 ,  H01L29/747 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device for protection from electrostatic discharge includes a number of modules for protection from electrostatic discharge. Each module includes a thyristor having terminals and a gate, and a diode coupled in antiparallel to the terminals of the thyristor. Each module is sized to share a saturation current with neighboring modules when an electrostatic discharge current is received. A resistive network couples modules between two terminals. A triggering circuit includes a common triggering output that is coupled to the gate of the thyristor of each module and a common buried semiconductor layer contacts each module.

Abstract translation: 用于防止静电放电的半导体器件包括用于防止静电放电的多个模块。 每个模块包括具有端子和栅极的晶闸管和与晶闸管的端子反平行耦合的二极管。 当接收到静电放电电流时，每个模块的大小与相邻模块共享饱和电流。 电阻网络在两个终端之间耦合模块。 触发电路包括耦合到每个模块的晶闸管的栅极的公共触发输出，并且公共掩埋半导体层接触每个模块。

公开(公告)号：US09454023B2

公开(公告)日：2016-09-27

申请号：US14638345

申请日：2015-03-04

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert Manouvrier

IPC: G02F1/035 ,  G02F1/295 ,  G02B6/12 ,  G02B6/10 ,  G02F1/025 ,  G02F1/225

CPC classification number: G02F1/025 ,  G02F1/0123 ,  G02F1/225 ,  G02F1/2255

Abstract: A semiconductor electro-optical phase shifter may include a substrate, an optical waveguide segment (12) formed on the substrate, and first and second zones of opposite conductivity types configured to form a first bipolar junction perpendicular to the substrate. The phase shifter may also include a dynamic control structure configured to reverse bias the first junction and a static control structure configured to direct a quiescent current in the second zone, parallel to the first junction.

Abstract translation: 半导体电光移相器可以包括衬底，形成在衬底上的光波导段（12）以及被配置为形成垂直于衬底的第一双极结的相反导电类型的第一和第二区。 移相器还可以包括被配置为反向偏置第一结的动态控制结构和被配置成引导平行于第一结的第二区中的静态电流的静态控制结构。

公开(公告)号：US09432008B2

公开(公告)日：2016-08-30

申请号：US14337896

申请日：2014-07-22

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Stéphane Le Tual ,  Pratap Narayan Singh

IPC: H03K5/13 ,  H03K5/134 ,  H03K5/00

CPC classification number: H03K5/134 ,  H03K5/13 ,  H03K2005/00032 ,  H03K2005/00208 ,  H03K2005/00215 ,  H03K2217/0018

Abstract: A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages, to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.

Abstract translation: 延迟电路包括第一和第二晶体管和偏置电路。 第一晶体管具有耦合到延迟电路的输入节点的控制节点，耦合到第一电源电压的第一主电流节点和耦合到延迟电路的输出节点的第二主电流节点。 第二晶体管具有耦合到输入节点的控制节点，耦合到第二电源电压的第一主电流节点和耦合到输出节点的第二主电流节点。 偏置电路被配置为产生第一和第二差分控制电压，以将第一差分控制电压施加到第一晶体管的另一控制节点，并将第二差分控制电压施加到第二晶体管的另一个控制节点。

公开(公告)号：US09431373B2

公开(公告)日：2016-08-30

申请号：US14572288

申请日：2014-12-16

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Rachid Taibi ,  Cédrick Chappaz ,  Lea Di Cioccio ,  Laurent-Luc Chapelon

IPC: H01L21/66 ,  H01L25/065 ,  H01L27/06

CPC classification number: H01L25/0657 ,  H01L22/12 ,  H01L22/14 ,  H01L27/0688 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06596

Abstract: A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations.

Abstract translation: 三维集成结构可以包括分别包括两条金属线的两个组装的集成电路，以及穿过集成电路中的一个的至少两个空腔，并分别与两个金属线电接触地分开开放到两个位置。 空腔的尺寸可以将测量装置放置在空腔的底部，并与两个位置电接触。

公开(公告)号：US20160238806A1

公开(公告)日：2016-08-18

申请号：US15140701

申请日：2016-04-28

Applicant: STMicroelectronics SA

Inventor： Pascal Fonteneau

IPC: G02B6/42 ,  H01L23/528 ,  H01L23/498 ,  H01L27/02 ,  H01L29/87 ,  G02B6/122 ,  H01L25/16

CPC classification number: G02B6/4275 ,  G02B6/122 ,  G02B6/428 ,  G02B2006/12061 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/60 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/167 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/87 ,  H01L2224/16235 ,  H01L2225/06534 ,  H01L2225/06572 ,  H01L2924/10253 ,  H01L2924/1431

Abstract: A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a first one of the chips is formed in a second one of the chips. Preferably, the chips are of SOI type, the second chip includes an SOI layer having a first thickness sufficient to support the component for protecting elements. The first chip also includes an SOI layer but having a second thickness smaller than the first thickness that is insufficient to support the component for protecting elements. The SOI layer of the second chip may be an optical waveguide layer.

Abstract translation: 一种装置包括彼此安装的集成电路芯片。 用于保护芯片中的第一芯片的元件的至少一个部件形成在第二芯片中。 优选地，芯片是SOI型的，第二芯片包括具有足以支撑用于保护元件的部件的第一厚度的SOI层。 第一芯片还包括SOI层，但是具有小于不足以支撑用于保护元件的部件的第一厚度的第二厚度。 第二芯片的SOI层可以是光波导层。

公开(公告)号：US09419634B1

公开(公告)日：2016-08-16

申请号：US14752226

申请日：2015-06-26

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Sebastien Dedieu ,  Abhirup Lahiri

IPC: H03L7/24 ,  H03K3/03

CPC classification number: H03K3/0315 ,  H03K3/013 ,  H03L1/02 ,  H03L7/00 ,  H03L7/0805 ,  H03L7/24

Abstract: A multiple phase oscillator includes a master oscillator that injection locks a first ring oscillator. The free-running frequency of the first ring oscillator is adjustable through a control signal. A second ring oscillator has a same structure as the first ring oscillator and is connected to operate in a free-running mode. The free-running frequency of the second ring oscillator is adjustable through the control signal. A control loop senses the output of the second ring oscillator and adjusts the control signal so that the free-running frequency of the second ring oscillator matches a desired value.

Abstract translation: 多相振荡器包括一个主振荡器，该主振荡器注入锁定第一个环形振荡器。 第一个环形振荡器的自由运行频率可通过控制信号进行调节。 第二环形振荡器具有与第一环形振荡器相同的结构，并连接以工作在自由运行模式。 第二个环形振荡器的自由运行频率可以通过控制信号进行调节。 控制回路感测第二环形振荡器的输出并调整控制信号，使得第二环形振荡器的自由运行频率与期望值相匹配。

公开(公告)号：US09411176B2

公开(公告)日：2016-08-09

申请号：US14492435

申请日：2014-09-22

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA

Inventor： Jean-Robert Manouvrier ,  Frédéric Boeuf

IPC: G02F1/025 ,  G02F1/225 ,  G02F1/21

CPC classification number: G02F1/025 ,  G02F1/225 ,  G02F2001/212

Abstract: An electro-optical phase shifter to be located in an optical waveguide may include a rib of a semiconductor material extending along a length of the optical waveguide and a control structure configured to modify a concentration of carriers in the rib according to a control voltage present between first and second control terminals of the phase shifter. The control structure may include a conductive layer covering a portion of the rib and electrically connected to a first of the control terminals. An insulating layer may be configured to electrically isolate the conductive layer from the rib.

Abstract translation: 位于光波导中的电光移相器可以包括沿着光波导的长度延伸的半导体材料的肋，以及控制结构，其被配置为根据存在于所述肋之间的控制电压来修改肋中的载流子的浓度 移相器的第一和第二控制端子。 控制结构可以包括覆盖肋的一部分并电连接到第一控制端的导电层。 绝缘层可以被配置为将导电层与肋电隔离。

公开(公告)号：US20160218098A1

公开(公告)日：2016-07-28

申请号：US15087622

申请日：2016-03-31

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Jean Jimenez

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0255 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/0292 ,  H01L29/7416 ,  H01L29/747 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device for protection from electrostatic discharge includes a number of modules for protection from electrostatic discharge. Each module includes a thyristor having terminals and a gate, and a diode coupled in antiparallel to the terminals of the thyristor. Each module is sized to share a saturation current with neighboring modules when an electrostatic discharge current is received. A resistive network couples modules between two terminals. A triggering circuit includes a common triggering output that is coupled to the gate of the thyristor of each module and a common buried semiconductor layer contacts each module.

Abstract translation: 用于防止静电放电的半导体器件包括用于防止静电放电的多个模块。 每个模块包括具有端子和栅极的晶闸管和与晶闸管的端子反平行耦合的二极管。 当接收到静电放电电流时，每个模块的大小与相邻模块共享饱和电流。 电阻网络在两个终端之间耦合模块。 触发电路包括耦合到每个模块的晶闸管的栅极的公共触发输出，并且公共掩埋半导体层接触每个模块。

公开(公告)号：US09379213B2

公开(公告)日：2016-06-28

申请号：US14450385

申请日：2014-08-04

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA

Inventor： Perrine Batude ,  Jean-Michel Hartmann ,  Benoit Sklenard ,  Maud Vinet

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/16 ,  H01L29/417 ,  H01L29/786 ,  H01L29/161 ,  H01L21/265 ,  H01L21/28

CPC classification number: H01L29/66568 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2807 ,  H01L21/28088 ,  H01L29/16 ,  H01L29/161 ,  H01L29/41766 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78654

Abstract: Method for fabricating a transistor comprising the steps consisting of: forming sacrificial zones in a semi-conductor layer, either side of a transistor channel zone, forming insulating spacers on said sacrificial zones against the sides of the gate of said transistor, removing said sacrificial zones so as to form cavities, with the cavities extending on either side of said channel zone and penetrating under said spacers, forming doped semi-conductor material in said cavities, with said semi-conductor material penetrating under said spacers.

Abstract translation: 晶体管的制造方法，包括以下步骤：在晶体管沟道区的任一侧的半导体层中形成牺牲区，在所述牺牲区上形成抵靠所述晶体管的栅极的侧面的绝缘间隔物，去除所述牺牲区 以便形成空腔，其中所述空腔在所述通道区域的任一侧上延伸并且穿过所述间隔件，在所述空腔中形成掺杂的半导体材料，所述半导体材料穿透在所述间隔件下方。

公开(公告)号：US09372354B2

公开(公告)日：2016-06-21

申请号：US14182033

申请日：2014-02-17

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert Manouvrier

IPC: G02F1/01 ,  G02F1/025 ,  G01J9/00 ,  G01J9/02 ,  H04B10/50 ,  G02F1/21

CPC classification number: G02F1/0123 ,  G01J9/00 ,  G01J9/02 ,  G02F1/025 ,  G02F1/218 ,  G02F1/2257 ,  G02F2001/212 ,  G02F2201/58 ,  G02F2203/50 ,  H04B10/5053 ,  H04B10/50575

Abstract: An optical modulator uses an optoelectronic phase comparator configured to provide, in the form of an electrical signal, a measure of a phase difference between two optical waves. The phase comparator includes an optical directional coupler having two coupled channels respectively defining two optical inputs for receiving the two optical waves to be compared. Two photodiodes are configured to respectively receive the optical output powers of the two channels of the directional coupler. An electrical circuit is configured to supply, as a measure of the optical phase shift, an electrical signal proportional to the difference between the electrical signals produced by the two photodiodes.

Abstract translation: 光调制器使用光电相位比较器，其被配置为以电信号的形式提供两个光波之间的相位差的量度。 相位比较器包括具有两个耦合通道的光学定向耦合器，该耦合通道分别限定用于接收要比较的两个光波的两个光学输入。 两个光电二极管被配置为分别接收定向耦合器的两个通道的光输出功率。 电路被配置为提供与两个光电二极管产生的电信号之间的差成比例的电信号作为光相移的测量。