公开(公告)号：US09520334B2

公开(公告)日：2016-12-13

申请号：US14155007

申请日：2014-01-14

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  Anne Lombardot

Inventor： Laurent-Luc Chapelon ,  Pascal Ancey ,  Sandrine Lhostis

IPC: H01L23/34 ,  H01L23/36 ,  H01L23/427 ,  H01L23/433 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L29/06

CPC classification number: H01L23/36 ,  H01L23/3128 ,  H01L23/4275 ,  H01L23/4334 ,  H01L23/481 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589

Abstract: An integrated structure includes a support supporting at least one chip and a heat dissipating housing, attached to the chip. The housing is thermally conductive and has a thermal expansion compatible with the chip. The housing may further including closed cavities filled with a phase change material.

Abstract translation: 集成结构包括支撑至少一个芯片的支撑件和附接到芯片的散热壳体。 壳体是导热的并具有与芯片兼容的热膨胀。 壳体还可以包括填充有相变材料的封闭空腔。

公开(公告)号：US09431373B2

公开(公告)日：2016-08-30

申请号：US14572288

申请日：2014-12-16

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Rachid Taibi ,  Cédrick Chappaz ,  Lea Di Cioccio ,  Laurent-Luc Chapelon

IPC: H01L21/66 ,  H01L25/065 ,  H01L27/06

CPC classification number: H01L25/0657 ,  H01L22/12 ,  H01L22/14 ,  H01L27/0688 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06596

Abstract: A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations.

Abstract translation: 三维集成结构可以包括分别包括两条金属线的两个组装的集成电路，以及穿过集成电路中的一个的至少两个空腔，并分别与两个金属线电接触地分开开放到两个位置。 空腔的尺寸可以将测量装置放置在空腔的底部，并与两个位置电接触。

公开(公告)号：US20140210071A1

公开(公告)日：2014-07-31

申请号：US14155007

申请日：2014-01-14

Applicant: Anne Lombardot ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Laurent-Luc Chapelon ,  Pascal Ancey ,  Sandrine Lhostis

IPC: H01L23/36

CPC classification number: H01L23/36 ,  H01L23/3128 ,  H01L23/4275 ,  H01L23/4334 ,  H01L23/481 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589

Abstract: An integrated structure includes a support supporting at least one chip and a heat dissipating housing, attached to the chip. The housing is thermally conductive and has a thermal expansion compatible with the chip. The housing may further including closed cavities filled with a phase change material.

Abstract translation: 集成结构包括支撑至少一个芯片的支撑件和附接到芯片的散热壳体。 壳体是导热的并具有与芯片兼容的热膨胀。 壳体还可以包括填充有相变材料的封闭空腔。

公开(公告)号：US08916393B2

公开(公告)日：2014-12-23

申请号：US13624214

申请日：2012-09-21

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Rachid Taibi ,  Cedrick Chappaz ,  Lea Di Cioccio ,  Laurent-Luc Chapelon

IPC: H01L21/66 ,  H01L27/06

CPC classification number: H01L25/0657 ,  H01L22/12 ,  H01L22/14 ,  H01L27/0688 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06596

Abstract: A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations.

Abstract translation: 三维集成结构可以包括分别包括两条金属线的两个组装的集成电路，以及穿过集成电路中的一个的至少两个空腔，并分别与两个金属线电接触地分开开放到两个位置。 空腔的尺寸可以将测量装置放置在空腔的底部，并与两个位置电接触。

公开(公告)号：US12218163B2

公开(公告)日：2025-02-04

申请号：US18591950

申请日：2024-02-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael Fourel ,  Laurent-Luc Chapelon

IPC: H01L27/146 ,  G02B1/10 ,  G02B1/14 ,  G02B3/00

Abstract: An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.

公开(公告)号：US11948950B2

公开(公告)日：2024-04-02

申请号：US17224720

申请日：2021-04-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael Fourel ,  Laurent-Luc Chapelon

IPC: H01L27/146 ,  G02B1/10 ,  G02B1/14 ,  G02B3/00

CPC classification number: H01L27/14621 ,  G02B1/10 ,  G02B1/14 ,  G02B3/0012 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14685

Abstract: An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.

公开(公告)号：US20150287689A1

公开(公告)日：2015-10-08

申请号：US14743072

申请日：2015-06-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon ,  Julien Cuzzocrea

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/48

CPC classification number: H01L24/13 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/0501 ,  H01L2224/0502 ,  H01L2224/05099 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/0556 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/13657 ,  H01L2224/13684 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.

Abstract translation: 集成电路芯片包括衬底管芯和集成电路以及形成在衬底管芯的正面上的前部电互连网络的层。 由导电材料制成的本地电连接通孔形成在基板模具的孔中。 通孔连接到电互连网络的连接部分。 由导电材料制成的电连接柱形成在电连接通孔的后部。 局部外部保护层至少部分地覆盖电连接通孔和电连接柱。

公开(公告)号：US20140015088A1

公开(公告)日：2014-01-16

申请号：US13934683

申请日：2013-07-03

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon

IPC: H01L27/04

CPC classification number: H01L27/04 ,  G01K5/56 ,  H01L22/34 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/08057 ,  H01L2224/08111 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80012 ,  H01L2224/80097 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: A three-dimensional integrated structure is formed from a first integrated circuit with a first cavity filled with a first conductive material and a second integrated circuit with a second cavity filled with a second conductive material, the second cavity facing the first cavity. The filled first cavity forms a first element and the filled second cavity forms a second element, the first and second elements separated from each other by a cavity. The first and second conductive materials have different thermal expansion coefficients. A contact detection circuit is electrically connected to the filled first and second cavities, and is operable to sense electrical contact between the first and second conductive materials in response to a change in temperature.

Abstract translation: 三维集成结构由具有填充有第一导电材料的第一空腔的第一集成电路和具有填充有第二导电材料的第二空腔的第二集成电路形成，第二空腔面对第一空腔。 填充的第一空腔形成第一元件，并且填充的第二空腔形成第二元件，第一元件和第二元件通过空腔彼此分离。 第一和第二导电材料具有不同的热膨胀系数。 接触检测电路电连接到填充的第一和第二空腔，并且可操作以响应于温度变化来感测第一和第二导电材料之间的电接触。

公开(公告)号：US20130292823A1

公开(公告)日：2013-11-07

申请号：US13869072

申请日：2013-04-24

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Laurent-Luc Chapelon

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5384 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81141 ,  H01L2224/81815 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20754 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.

公开(公告)号：US20130181220A1

公开(公告)日：2013-07-18

申请号：US13624214

申请日：2012-09-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Rachid Taibi ,  Cedrick Chappaz ,  Lea Di Cioccio ,  Laurent-Luc Chapelon

IPC: H01L21/66

CPC classification number: H01L25/0657 ,  H01L22/12 ,  H01L22/14 ,  H01L27/0688 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06596

Abstract: A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations.