公开(公告)号：US20240320086A1

公开(公告)日：2024-09-26

申请号：US18612421

申请日：2024-03-21

Applicant: STMicroelectronics International N.V.

Inventor： Pierre-Alexandre BLANC ,  Gilles VAN ASSCHE

IPC: G06F11/10 ,  G06F21/60

CPC classification number: G06F11/1004 ,  G06F11/1068 ,  G06F21/602

Abstract: The present description concerns a method of checking a first data element, executed by an electronic device comprising a processor and a memory, wherein said first data element is not stored in said memory and is divided in N second data elements independent from the first data element, each second data element being stored in said memory, and a result of an application of a XOR function to the N second elements being equal to the first data element, wherein an image of the first data element by a CRC function linear with respect to the XOR function is stored in said memory, and said method comprising a step, executed by said processor, of checking if said image of the first data element by said CRC function is equal to an application of the XOR function to the images of N second elements by said CRC function.

公开(公告)号：US12093193B2

公开(公告)日：2024-09-17

申请号：US17067967

申请日：2020-10-12

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Rupesh Singh

IPC: G06F13/16 ,  G06F7/487 ,  G06F9/30 ,  G06F17/16

CPC classification number: G06F13/1668 ,  G06F7/4876 ,  G06F9/3001 ,  G06F9/30021 ,  G06F17/16

Abstract: Individual bits of a K bit unary data word, wherein K is greater than one, are applied to K polyphase finite impulse response filter circuits. Each polyphase finite impulse response filter circuit receives a different bit and operates with a single bit precision to generate from each received bit a filtered output data word. A gain adjustment is applied by a gain stage circuit to each filtered output data word to generate a corresponding gain adjusted output data word. The gain adjusted output data words from the gain stage circuits are summed to generate an output data word. The unary data word may be output from a source such as a data encoder or a quantizer.

公开(公告)号：US20240304713A1

公开(公告)日：2024-09-12

申请号：US18591344

申请日：2024-02-29

Applicant: STMicroelectronics International N.V.

Inventor： Ferdinando IUCOLANO ,  Aurore CONSTANT ,  Cristina TRINGALI ,  Maria Eloisa CASTAGNA

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462

Abstract: An HEMT device is formed on a semiconductor body having a semiconductive heterostructure. A control region of a semiconductor material, is arranged on the semiconductor body and has a top surface and lateral sides. A control terminal, of conductive material, extends on and in contact with the top surface of the control region. A passivation layer of non-conductive material, extends on the semiconductor body, partially on the top surface of the control region and on the lateral sides of the control region, laterally and at a distance from the control terminal.

公开(公告)号：US20240302219A1

公开(公告)日：2024-09-12

申请号：US18182058

申请日：2023-03-10

Applicant: STMicroelectronics International N.V.

Inventor： Federico VERCESI ,  Silvia NICOLI ,  Cinzia DE MARCO

IPC: G01K7/01 ,  H01L23/485 ,  H01L23/522

CPC classification number: G01K7/015 ,  H01L23/485 ,  H01L23/5226

Abstract: Disclosed herein are thermal sensor devices including TMOS devices with a mass suspended over a cavity by springs extending between a frame and the mass. The thermal sensor devices include stoppers that limit upward and/or downward movement of the springs and therefore the mass. These stoppers are formed from sidewalls supporting a top cap over the frame, springs, and mass. The stoppers are constructed by using various overlapping metal layers during fabrication. Details of forming the stoppers using these overlapping metal layers are contained here.

公开(公告)号：US20240297249A1

公开(公告)日：2024-09-05

申请号：US18583748

申请日：2024-02-21

Applicant: STMicroelectronics International N.V.

Inventor： Alfio GUARNERA ,  Mario Giuseppe SAGGIO ,  Cateno Marco CAMALLERI ,  Edoardo ZANETTI

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/7811 ,  H01L21/0465 ,  H01L29/0603 ,  H01L29/1608

Abstract: Method of manufacturing an electronic device, comprising the steps of: arranging a semiconductor body of N-type, having a lattice structure with spatial symmetry, comprising an active area an edge region surrounding the active area; forming, in the edge region, an intentionally damaged region wherein the lattice structure has no spatial symmetry; forming an edge termination region of P-type at the damaged region, by random implant; forming a current spreading layer, CSL, in the edge region at and lateral to the damaged region, by channeled implant. The CSL has, at the damaged region, a minimum thickness and, laterally to the damaged region, a maximum thickness. The minimum thickness is lower than the thickness of the edge termination region.

公开(公告)号：US20240297240A1

公开(公告)日：2024-09-05

申请号：US18428306

申请日：2024-01-31

Applicant: STMicroelectronics International N.V.

Inventor： Voon Cheng NGWAN ,  Churn Weng YIM ,  Vincenzo ENEA

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/66734 ,  H01L29/401 ,  H01L29/407 ,  H01L29/7813

Abstract: A semiconductor substrate has a substrate trench extending from a front surface and including a lower part and an upper part. A first insulation layer lines the substrate trench, and a first conductive material is insulated from the semiconductor substrate by the first insulating layer to form a transistor field plate electrode. A gate trench in the first insulation layer defines an integral part of the first insulating layer surrounding the first conductive material in an upper part of the substrate trench. A second insulating layer lines the semiconductor substrate at the upper part of the substrate trench in the gate trench. A second conductive material fills the gate. The second conductive material forms a transistor gate electrode that is insulated from the semiconductor substrate by the second insulating layer and further insulated from the first conductive material by the integral part of the first insulating layer.

公开(公告)号：US20240296899A1

公开(公告)日：2024-09-05

申请号：US18661914

申请日：2024-05-13

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Balwinder Singh SONI ,  Avneep Kumar GOYAL

IPC: G11C29/38 ,  G11C7/10 ,  G11C7/22 ,  G11C29/12 ,  G11C29/14 ,  G11C29/36 ,  H03K19/20

CPC classification number: G11C29/38 ,  G11C7/1084 ,  G11C7/22 ,  G11C29/14 ,  G11C29/36 ,  G11C2029/1206 ,  G11C2029/3602 ,  H03K19/20

Abstract: A system includes a write-data register and a read-data register, each clocked by a clock signal, and a first-in-first-out (FIFO) buffer coupled between the write-data register and the read-data register, the FIFO buffer including latches configured to store data. The system further includes glue logic with first, second, and third logic circuits configured to generate an internal write enable signal, an internal read valid signal, and an internal read enable signal based on an operational mode of the system. The system is configured to be selectively switched between a normal operational mode, where the latches are accessed for reading and writing by a read enable signal and write enable signal based on a read address signal and a write address signal, and a transition testing mode, where the latches are tested using the internal write enable signal, the internal read enable signal, and the internal read valid signal.

公开(公告)号：US20240289148A1

公开(公告)日：2024-08-29

申请号：US18582274

申请日：2024-02-20

Applicant: STMicroelectronics International N.V.

Inventor： Luigi DI MAGGIO ,  Ettore MIRTO

IPC: G06F9/455 ,  G06F9/54

CPC classification number: G06F9/45529 ,  G06F9/54

Abstract: A method includes executing an application of a scripting language. The application of the scripting language uses first and second packages of an application programming interface (API). The first and second packages extend to each other. The method includes, from a class of the first package, calling and executing first native code of the API to implement a function of a method of the class of the first package. The first native code is in a programming language different from the scripting language. The executing the first native code of the API includes calling a method of a class of the second package. The called method of the class of the second package is executed using a virtual machine of the scripting language. The application of the scripting language may be a Java card application, and the programming language may be a C programming language.

公开(公告)号：US20240288478A1

公开(公告)日：2024-08-29

申请号：US18436644

申请日：2024-02-08

Applicant: STMicroelectronics International N.V.

Inventor： Antonio Barcella ,  Mario Rotigni ,  Nicolas Bernard Grossier

IPC: G01R23/00 ,  G01S19/13 ,  H03K5/26 ,  H03K19/20

CPC classification number: G01R23/005 ,  G01S19/13 ,  H03K5/26 ,  H03K19/20

Abstract: A method comprises receiving an input clock signal having a clock frequency band between a lower frequency limit value and an upper frequency limit value, dividing the clock frequency band in a set of frequency ranges having a set of frequency limit values that include the lower frequency limit value and the upper frequency limit value, comparing the frequency of the clock signal with the set of frequency limit values to produce comparison indicators having a first logic value when the measured frequency fails to exceed at least one frequency limit value and having a second logic value when the measured frequency exceeds the at least one frequency limit value, and, as a result of at least one of the logic values of comparison indicators having the second logic value, producing a global flag signal indicating that the measured frequency falls outside of a frequency range.

公开(公告)号：US20240283736A1

公开(公告)日：2024-08-22

申请号：US18440216

申请日：2024-02-13

Applicant: STMicroelectronics International N.V.

Inventor： Lorenzo Re Fiorentin ,  Giampiero Borgonovo ,  Gianluca Di Carlo

IPC: H04L45/00 ,  H04L45/745 ,  H04L61/2546

CPC classification number: H04L45/566 ,  H04L45/745 ,  H04L61/2546

Abstract: A hardware network accelerator comprises a plurality of Ethernet communication interfaces, a plurality of memories, and a further memory. Each memory stores records comprising destination IP data identifying a destination IP address range. The further memory stores further records, wherein each record comprises next-hop data indicating a next-hop IP address, next-hop enable data, and network port data indicating an Ethernet communication interface. Each Ethernet communication interface is configured to obtain an IP packet, access in parallel the memories in order to read the records, select a record having a destination IP address range containing the destination IP address of the IP packet, read the further record associated with the selected record from the further memory, and select the indicated Ethernet communication interface. The selected Ethernet communication interface is configured to transmit an Ethernet frame comprising the IP packet based on the next-hop enable data and next-hop data.