公开(公告)号：US07537984B2

公开(公告)日：2009-05-26

申请号：US11641507

申请日：2006-12-19

申请人： Jeff D. Bude ,  Peide Ye ,  Kwok K. Ng ,  Bin Yang

发明人： Jeff D. Bude ,  Peide Ye ,  Kwok K. Ng ,  Bin Yang

IPC分类号： H01L21/338

CPC分类号： H01L29/4983 ,  H01L29/812

摘要： A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel. The overlapping gate/field plate or p-type pocket extend into the drift region of the device, controlling the electrical potential of the device in a manner that provides the desired control of the electrical potential in the drift region.

摘要翻译： 公开了一种配置用于大功率应用的场效应晶体管及其制造方法。 场效应晶体管由III-V材料形成，并且被配置为具有对大功率应用有利的击穿电压。 通过确定该工作电压的工作电压和期望的击穿电压来配置场效应晶体管。 然后识别与工作电压和期望的击穿电压相关联的峰值电场。 然后将该器件配置为在该工作电压下呈现鉴定的峰值电场。 通过选择控制器件漂移区域中的电位的器件特征来实现该器件的配置。 这些特征包括使用重叠的栅极或场板结合覆盖器件沟道的势垒层，或形成在器件沟道下形成的单晶III-V材料区域中的p型阱。 重叠的栅极/场板或p型阱延伸到器件的漂移区域中，以提供对漂移区域中的电势的期望控制的方式控制器件的电位。

公开(公告)号：US20090128468A1

公开(公告)日：2009-05-21

申请号：US12005714

申请日：2007-12-28

申请人： Bin Yang ,  Gang-Qiang Zheng ,  Jian-Ying Lan

发明人： Bin Yang ,  Gang-Qiang Zheng ,  Jian-Ying Lan

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G3/2092

摘要： An exemplary liquid crystal module (20) includes liquid crystal panel (200) and a driving chip (210). The driving chip includes an interface circuit (230), a storing member (260), and a plurality of input ports. The plurality of input ports are configured for receiving display data. The storing member and the interface circuit share at least one common input port of the plurality of input ports. The storing member receives at least one mode selection signal for controlling a working mode of the driving chip via the at least one common input port in a first period of time. The storing member outputs the at least one mode selection signal to the interface circuit, and then the interface circuit receives the display data via the plurality of input ports including the at least one common input port according to the working mode in a second period of time.

摘要翻译： 示例性液晶模块（20）包括液晶面板（200）和驱动芯片（210）。 驱动芯片包括接口电路（230），存储部件（260）和多个输入端口。 多个输入端口被配置为用于接收显示数据。 存储构件和接口电路共享多个输入端口中的至少一个公共输入端口。 存储部件在第一时间段内经由至少一个公共输入端口接收用于控制驱动芯片的工作模式的至少一个模式选择信号。 存储构件将至少一个模式选择信号输出到接口电路，然后接口电路经由包括至少一个公共输入端口的多个输入端口在第二时间段内根据工作模式接收显示数据 。

公开(公告)号：US20090051972A1

公开(公告)日：2009-02-26

申请号：US11918077

申请日：2006-03-31

申请人： Zhihong Liu ,  Feng Chen ,  Bin Yang

发明人： Zhihong Liu ,  Feng Chen ,  Bin Yang

IPC分类号： H04N1/40

CPC分类号： H04N1/4052

摘要： The present invention relates to a method and apparatus capable of generating frequency-modulation halftone dots in high speed and belongs to the field of the digital image halftone. In the prior art, read-write operation is usually carried out many times in error rows during processing each pixel so that halftone dots are generated in low speed. In the method according to the present invention, the error generated by the current pixel is buffered in a register file and the final accumulated error values are written in the error rows only after all of the relative pixels are processed. Thus, read-write operation is carried out only once in the error rows for processing each pixel. The present invention also provides an apparatus to implement the method. The apparatus comprises an error row memory, an error buffer register file, a gray generation circuit, a threshold comparison circuit, an error generation circuit, an error buffer register file control circuit, and an error row control circuit. The method and apparatus according to the present invention decrease the steps in operation and improve the speed for generating the frequency-modulation halftone dots.

摘要翻译： 本发明涉及能够高速产生调频半色调点的属于数字图像半色调的领域的方法和装置。 在现有技术中，在处理每个像素期间，读写操作通常在错误行中进行多次，使得半色调点以低速生成。 在根据本发明的方法中，由当前像素产生的误差被缓存在寄存器文件中，并且只有在处理了所有相对像素之后才将最终的累积误差值写入误差行。 因此，在用于处理每个像素的错误行中仅执行一次读写操作。 本发明还提供了一种实现该方法的装置。 该装置包括错误行存储器，错误缓冲寄存器文件，灰色生成电路，阈值比较电路，错误产生电路，错误缓冲寄存器文件控制电路和错误行控制电路。 根据本发明的方法和装置降低了操作步骤，提高了生成调频半色调点的速度。

公开(公告)号：US20080286921A1

公开(公告)日：2008-11-20

申请号：US11748743

申请日：2007-05-15

申请人： Wen Yu ,  Paul Besser ,  Bin Yang ,  Haijiang Yu ,  Simon S. Chan

发明人： Wen Yu ,  Paul Besser ,  Bin Yang ,  Haijiang Yu ,  Simon S. Chan

IPC分类号： H01L21/8234

CPC分类号： H01L21/324 ,  H01L21/28052 ,  H01L29/66507 ,  H01L29/78

摘要： The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness.

摘要翻译： 形成器件的栅极和有源区，并且施加和去除氮化物和氧化物层的交替步骤允许在不同区域暴露硅，同时保持覆盖有氮化物的其它区域中的硅或多晶硅。 金属层沉积在暴露的硅或多晶硅上，退火在所选择的暴露区域中形成硅化物层。 氧化物层和/或氮化物层从被覆盖区域移除，另一个金属层被沉积​​。 在第二暴露区域上形成一层厚度的硅化物，并在先前的硅化物厚度上形成附加的硅化物厚度来重复退火工艺。

公开(公告)号：US20080003609A1

公开(公告)日：2008-01-03

申请号：US11801676

申请日：2007-05-10

申请人： Bin Yang

发明人： Bin Yang

IPC分类号： C12Q1/68

CPC分类号： C12Q1/6886 ,  C12Q2600/112 ,  C12Q2600/154 ,  C12Q2600/16

摘要： A diagnostic method for bladder urethelial carcinoma includes obtaining an isolated nucleotide sample from a subject and detecting the promoter methylation of at least three tumor suppressor genes selected form group consisting of DAPK, RAR-beta, p14, p73, MGMT, APC, SOCS-1, BRCA-1, and FHIT.

摘要翻译： 膀胱尿道上皮癌的诊断方法包括从受试者获得分离的核苷酸样品，并检测至少三种选自DAPK，RAR-β，p14，p73，MGMT，APC，SOCS-1的肿瘤抑制基因的启动子甲基化 ，BRCA-1和FHIT。

公开(公告)号：US20220341116A1

公开(公告)日：2022-10-27

申请号：US17725569

申请日：2022-04-21

申请人： Yuanqiang Cai ,  Jun Wang ,  Hongtao Fu ,  Shihu Gao ,  Bin Yang ,  Xiaoxiao Zhu ,  Rila Anda ,  Guohui Yuan

发明人： Yuanqiang Cai ,  Jun Wang ,  Hongtao Fu ,  Shihu Gao ,  Bin Yang ,  Xiaoxiao Zhu ,  Rila Anda ,  Guohui Yuan

IPC分类号： E02D3/10 ,  E02D3/12

摘要： A method for foundation consolidation combining vacuum preloading and geomembrane bag assembly loading, which comprises: digging a slurry pit, filling mud into the slurry pit and conducting vacuum preloading pumpdrainage for multiple times, laying the geomembrane bag assemblies above the soft slurry seam processed through vacuum preloading pumpdrainage inside the slurry pit to form a plurality of loading layers, and laying the geomembrane bag assemblies by piling geomembrane bags. In view of the engineering complexity and uneven settlement resulting from conventional vacuum preloading using slag loading, geomembrane bag for loading to overcome the adverse effects of slag loading. In the present invention, the drainage system and the geomembrane bag assemblies are laid out to fully leverage their perspective properties, so as to improve the transmission of vacuity in the whole soil mass, speed up the drainage rate, and increase the degree of consolidation.

公开(公告)号：US08854067B2

公开(公告)日：2014-10-07

申请号：US13594292

申请日：2012-08-24

申请人： Amol Joshi ,  Charlene Chen ,  John Foster ,  Zhendong Hong ,  Olov Karlsson ,  Bei Li ,  Dipankar Pramanik ,  Usha Raghuram ,  Mark Victor Raymond ,  Jingang Su ,  Bin Yang

发明人： Amol Joshi ,  Charlene Chen ,  John Foster ,  Zhendong Hong ,  Olov Karlsson ,  Bei Li ,  Dipankar Pramanik ,  Usha Raghuram ,  Mark Victor Raymond ,  Jingang Su ,  Bin Yang

IPC分类号： G01R27/08 ,  G01R31/28

CPC分类号： G01R27/08 ,  G01R31/2831 ,  H01L22/14 ,  H01L22/20

摘要： Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

摘要翻译： 描述了用于确定沉积在可与组合处理组合的半导体晶片上的导体的接触电阻率和肖特基势垒高度的方法和结构，从而允许同时测试许多处理条件和材料。 还描述了使用多环以及单环CTLM结构来消除寄生电阻的方法，以及用于在线监测性质的结构和方法。

公开(公告)号：US20140188417A1

公开(公告)日：2014-07-03

申请号：US13877317

申请日：2011-10-13

申请人： Xiuzhen Dong ,  Xuyang Huo ,  Fusheng You ,  Xuetao Shi ,  Feng Fu ,  Ruigang Liu ,  Zhenyu Ji ,  Canhua Xu ,  Bin Yang ,  Min Yang ,  Jiaxue Qi ,  Wen Zhang ,  Nan Wang

发明人： Xiuzhen Dong ,  Xuyang Huo ,  Fusheng You ,  Xuetao Shi ,  Feng Fu ,  Ruigang Liu ,  Zhenyu Ji ,  Canhua Xu ,  Bin Yang ,  Min Yang ,  Jiaxue Qi ,  Wen Zhang ,  Nan Wang

IPC分类号： G01R27/02

CPC分类号： G01R27/02 ,  A61B5/053 ,  A61B5/0536 ,  A61B5/7225 ,  G01R27/14

摘要： An electrical impedance detecting device of a portable electrical impedance imaging system by utilizing a theory of sending excitation signal and detecting response signal and a method thereof, wherein the excitation signal is a constant square wave excitation current signal, the response voltage signal on a target is transformed to a square wave signal with appropriate amplitudes by buffering, amplifying, RC filtering and differential amplifying circuits, and then is transformed to a digital signal at a proper time by an analog-to-digital converter. The response voltage signal is sampled once when at high level and once when at low level for every circle of the square wave signal by the ADC, and a sample V1 and a sample V2 are obtained respectively, difference of the sample V1 and the sample V2 is taken as a detecting result for one circle. An average value of the detecting result from a plurality of circles may be taken as a final result. Information of electrical impedance is illustrated by the final result because the excitation current signal is constant.

摘要翻译： 一种通过利用发送激励信号和检测响应信号的理论的便携式电阻抗成像系统的电阻抗检测装置及其方法，其中激励信号是恒定方波激励电流信号，目标上的响应电压信号是 通过缓冲，放大，RC滤波和差分放大电路转换成具有适当幅度的方波信号，然后通过模拟 - 数字转换器在适当的时间转换为数字信号。 响应电压信号在高电平时被采样一次，一旦在ADC的每个圆波信号的低电平处被采样一次，并且分别获得样本V1和样本V2，样本V1和样本V2的差 作为一个圆的检测结果。 可以将来自多个圆的检测结果的平均值作为最终结果。 由于激励电流信号是恒定的，所以最终结果说明了电阻抗的信息。

公开(公告)号：US20140132992A1

公开(公告)日：2014-05-15

申请号：US14128351

申请日：2012-05-18

申请人： Haifeng Li ,  Bin Yang

发明人： Haifeng Li ,  Bin Yang

IPC分类号： G06K15/02

CPC分类号： G06K15/1881 ,  H04N1/40087 ,  H04N1/4055

摘要： The present application discloses a method and an apparatus for generating multi-bit depth halftone amplitude-modulation dots. The method may comprise: scanning an input image to obtain a value of a current pixel Pxy, where x represents a lateral position index of the current pixel, and y represents a vertical position index of the current pixel; obtaining gj from a preset multi-bit depth threshold matrix G by starting with i=0, and determining if Pxy

摘要翻译： 本申请公开了一种用于产生多位深度半色调幅度调制点的方法和装置。 该方法可以包括：扫描输入图像以获得当前像素Pxy的值，其中x表示当前像素的横向位置索引，y表示当前像素的垂直位置索引; 通过以i = 0开始从预设的多位深度阈值矩阵G获得gj，并且确定Pxy

公开(公告)号：US08680624B2

公开(公告)日：2014-03-25

申请号：US13488109

申请日：2012-06-04

申请人： Man Fai Ng ,  Bin Yang

发明人： Man Fai Ng ,  Bin Yang

IPC分类号： H01L21/70 ,  H01L27/088 ,  H01L29/06

CPC分类号： H01L21/84 ,  H01L21/76267 ,  H01L21/823878 ,  H01L29/66772

摘要： Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.

摘要翻译： 提供了用于制造在绝缘材料区域内具有阻挡区域的半导体器件的方法和装置，导致从绝缘材料区域的脱气路径。 一种方法包括在靠近半导体材料的隔离区域的绝缘材料内形成阻挡区域，并形成覆盖半导体材料的隔离区域的栅极结构。 阻挡区域与半导体材料的隔离区域相邻，导致绝缘材料内的除气路径。