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    Buried metal-semiconductor alloy layers and structures and methods for fabrication thereof
    104.
    发明授权
    Buried metal-semiconductor alloy layers and structures and methods for fabrication thereof 有权
    埋地金属 - 半导体合金层及其制造方法及其制造方法

    公开(公告)号：US08759213B2

    公开(公告)日：2014-06-24

    申请号：US13607869

    申请日：2012-09-10

    申请人： Christian Lavoie ,  Francois Pagette ,  Anna W. Topol

    发明人： Christian Lavoie ,  Francois Pagette ,  Anna W. Topol

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/53271 ,  H01L21/743 ,  H01L21/76243 ,  H01L21/76889 ,  H01L21/84 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/78603 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.

    摘要翻译： 一种形成金属 - 半导体合金层的方法使用特定的热退火条件，通过掩埋半导体材料层和接触掩埋半导体材料层的金属 - 半导体合金形成金属层的相互扩散来提供无应力的金属 - 半导体合金层， 穿过覆盖层的孔，其下埋有半导体材料层。 所得到的半导体结构包括还包括覆盖层下面的互连部分的金属 - 半导体合金层和至少部分地穿过覆盖层的连续通孔部分。 这种金属 - 半导体合金层可以位于衬底和具有有源掺杂区域的半导体器件之间。

    RAISED SILICIDE CONTACT
    106.
    发明申请
    RAISED SILICIDE CONTACT 有权
    提高硅胶接触

    公开(公告)号：US20130334693A1

    公开(公告)日：2013-12-19

    申请号：US13525401

    申请日：2012-06-18

    申请人： Emre Alptekin ,  Nathaniel Berliner ,  Christian Lavoie ,  Kam-Leung Lee ,  Ahmet Serkan Ozcan

    发明人： Emre Alptekin ,  Nathaniel Berliner ,  Christian Lavoie ,  Kam-Leung Lee ,  Ahmet Serkan Ozcan

    IPC分类号： H01L23/532 ,  H01L21/768

    CPC分类号： H01L21/28518 ,  H01L21/02063 ,  H01L21/28525 ,  H01L21/76814 ,  H01L21/823814 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66575 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a raised silicide contact, the method including depositing a layer of silicon using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° and holding the temperature for about 0.1 miliseconds to about 600 seconds in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.

    摘要翻译： 一种用于形成硅化物接触的方法，所述方法包括使用气体簇注入技术沉积硅层，所述气体簇注入技术加速硅原子簇，使得它们穿过硅化物的顶表面上的表面氧化物; 将包括硅层的硅化物加热到约300℃至约950℃的温度，并在惰性气氛中保持约0.1毫秒至约600秒的温度，从而使来自硅层的硅部分地与剩余的硅化物部分地反应 形成在含硅衬底中; 以及从所述硅层形成凸起的硅化物，其中所述凸起的硅化物的厚度大于所述硅化物的厚度，并且所述硅化物在所述含硅衬底的顶表面上方突出。

    Schottky FET fabricated with gate last process
    107.
    发明授权
    Schottky FET fabricated with gate last process 有权
    用最后一道工艺制造的肖特基FET

    公开(公告)号：US08541835B2

    公开(公告)日：2013-09-24

    申请号：US13571429

    申请日：2012-08-10

    申请人： Jin Cai ,  Dechao Guo ,  Marwan H. Khater ,  Christian Lavoie ,  Zhen Zhang

    发明人： Jin Cai ,  Dechao Guo ,  Marwan H. Khater ,  Christian Lavoie ,  Zhen Zhang

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621

    摘要： A field effect transistor (FET) includes a semiconductor on insulator substrate, the substrate comprising a top semiconductor layer; source and drain regions located in the top semiconductor layer; a channel region located in the top semiconductor layer between the source region and the drain region, the channel region having a thickness that is less than a thickness of the source and drain regions; a gate located over the channel region; and a supporting material located over the source and drain regions adjacent to the gate.

    摘要翻译： 场效应晶体管（FET）包括绝缘体上半导体衬底，所述衬底包括顶部半导体层; 源极和漏极区域位于顶部半导体层中; 位于源极区域和漏极区域之间的顶部半导体层中的沟道区域，沟道区域的厚度小于源极和漏极区域的厚度; 位于通道区域上方的门; 以及位于与栅极相邻的源极和漏极区域之上的支撑材料。

    Use of Band Edge Gate Metals as Source Drain Contacts
    108.
    发明申请
    Use of Band Edge Gate Metals as Source Drain Contacts 有权
    使用带边缘栅极金属作为源极漏极触点

    公开(公告)号：US20130241008A1

    公开(公告)日：2013-09-19

    申请号：US13611736

    申请日：2012-09-12

    申请人： Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

    发明人： Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7833 ,  H01L21/28512 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

    摘要： A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.

    摘要翻译： 一种器件包括形成在半导体衬底中的沟道上方的栅叠层。 栅极堆叠包括栅极绝缘体材料层，覆盖栅极绝缘体材料层的栅极金属层和覆盖层带边缘栅极金属的接触金属层。 该装置还包括邻近通道的源极和漏极接触。 源极和漏极触点各自包括覆盖并与半导体衬底的掺杂区域直接电接触的栅极金属层以及覆盖在栅极金属层上的接触金属层。

    USE OF BAND EDGE GATE METALS AS SOURCE DRAIN CONTACTS
    109.
    发明申请
    USE OF BAND EDGE GATE METALS AS SOURCE DRAIN CONTACTS 审中-公开
    使用带边缘金属作为源漏联系

    公开(公告)号：US20130241007A1

    公开(公告)日：2013-09-19

    申请号：US13421276

    申请日：2012-03-15

    申请人： Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

    发明人： Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

    IPC分类号： H01L29/78 ,  H01L21/283

    CPC分类号： H01L29/7833 ,  H01L21/28512 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

    摘要： A method includes providing a semiconductor substrate having intentionally doped surface regions, the intentionally doped surface regions corresponding to locations of a source and a drain of a transistor; depositing a layer a band edge gate metal onto a gate insulator layer in a gate region of the transistor while simultaneously depositing the band edge gate metal onto the surface of the semiconductor substrate to be in contact with the intentionally doped surface regions; and depositing a layer of contact metal over the band edge gate metal in the gate region and in the locations of the source and the drain. The band edge gate metal in the source/drain regions reduces a Schottky barrier height of source/drain contacts of the transistor and serves to reduce contact resistance. A transistor fabricated in accordance with the method is also described.

    摘要翻译： 一种方法包括提供具有有意掺杂的表面区域的半导体衬底，有意掺杂的表面区域对应于晶体管的源极和漏极的位置; 在晶体管的栅极区域中的栅绝缘体层上沉积带边缘栅极金属层，同时将带边缘栅极金属沉积到半导体衬底的表面上以与有意掺杂的表面区域接触; 以及在所述栅极区域中以及所述源极和漏极的位置中的所述带边缘栅极金属之上沉积接触金属层。 源极/漏极区域中的带边缘栅极金属降低了晶体管的源极/漏极接触的肖特基势垒高度，并且用于降低接触电阻。 还描述了根据该方法制造的晶体管。