公开(公告)号：US09312183B1

公开(公告)日：2016-04-12

申请号：US14531743

申请日：2014-11-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Min Gyu Sung

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/1083 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer. A portion of the isolation fill and the capping layer is removed to expose an upper surface portion of the fin. Tapping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layer.

Abstract translation: 用于形成具有用于减少穿通漏电的封盖层的FinFET的方法包括提供具有设置在半导体衬底上的半导体衬底和鳍的中间半导体结构。 覆盖层设置在翅片上方，并且隔离填充物设置在覆盖层上。 去除隔离填充物和覆盖层的一部分以露出翅片的上表面部分。 突出层和鳍的下部限定了界面偶极层势垒，所述覆盖层的一部分可操作以提供增加的负电荷或增加与所述鳍相邻的正电荷，以减少与不具有 盖层。

公开(公告)号：US09293333B2

公开(公告)日：2016-03-22

申请号：US13944403

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Hoon Kim

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/28088 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795

Abstract: An improved method and structure for fabrication of replacement metal gate (RMG) field effect transistors is disclosed. P-type field effect transistor (PFET) gate cavities are protected while N work function metals are deposited in N-type field effect transistor (NFET) gate cavities.

Abstract translation: 公开了用于制造替代金属栅极（RMG）场效应晶体管的改进的方法和结构。 P型场效应晶体管（PFET）栅极腔被保护，而N型功能金属沉积在N型场效应晶体管（NFET）栅极腔中。

公开(公告)号：US09245968B2

公开(公告)日：2016-01-26

申请号：US14476073

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Kisik Choi ,  Chanro Park

IPC: H01L21/02 ,  H01L29/49 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor.

Abstract translation: 公开了一种改进的场效应晶体管及其制造方法。 在栅腔的基底和侧壁中形成阻挡层堆叠。 阻挡层堆叠具有第一金属层和第二金属层。 栅极电极金属沉积在空腔中。 阻挡层堆叠在栅极腔的侧壁上变薄或去除，以更精确地控制场效应晶体管的电压阈值。

公开(公告)号：US20150137373A1

公开(公告)日：2015-05-21

申请号：US14081749

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Xiuyu Cai ,  Hoon Kim

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76855 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits with improved contact structures and methods for fabricating integrated circuits with improved contact structures are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a device in and/or on a semiconductor substrate. Further, the method includes forming a contact structure in electrical contact with the device. The contact structure includes silicate barrier portions overlying the device, a barrier metal overlying the device and positioned between the silicate barrier portions, and a fill metal overlying the barrier metal and positioned between the silicate barrier portions.

Abstract translation: 提供具有改进的接触结构的集成电路和用于制造具有改进的接触结构的集成电路的方法。 在示例性实施例中，用于制造集成电路的方法包括在半导体衬底内和/或半导体衬底上提供器件。 此外，该方法包括形成与该装置电接触的接触结构。 接触结构包括覆盖该装置的硅酸盐阻挡部分，覆盖该装置并且位于硅酸盐阻挡部分之间的阻挡金属以及覆盖该阻挡金属并位于硅酸盐阻挡部分之间的填充金属。

公开(公告)号：US20150126023A1

公开(公告)日：2015-05-07

申请号：US14069782

申请日：2013-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kisik Choi ,  Hoon Kim

IPC: H01L21/28 ,  H01L29/51

CPC classification number: H01L21/28158 ,  H01L21/28185 ,  H01L21/28247 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes removing sacrificial gate structures for NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, forming a high-k gate insulation layer in the NMOS and PMOS gate cavities, forming a lanthanide-based material layer on the high-k gate insulation layer in the NMOS and PMOS gate cavities, performing a heating process to drive material from the lanthanide-based material layer into the high-k gate insulation layer so as to thereby form a lanthanide-containing high-k gate insulation layer in each of the NMOS and PMOS gate cavities, and forming gate electrode structures above the lanthanide-containing high-k gate insulation layer in the NMOS and PMOS gate cavities.

Abstract translation: 本文公开的一种说明性方法包括去除用于NMOS和PMOS晶体管的牺牲栅极结构，从而限定NMOS和PMOS栅极空腔，在NMOS和PMOS栅极腔中形成高k栅绝缘层，在高层上形成镧系元素基材料层 -k栅极绝缘层，执行加热处理以将材料从镧系元素基材料层驱动到高k栅极绝缘层中，从而形成含镧系元素的高k栅极绝缘层 在每个NMOS和PMOS栅极腔中，以及在NMOS和PMOS栅极腔中的含镧系元素的高k栅极绝缘层之上形成栅电极结构。

公开(公告)号：US20150108577A1

公开(公告)日：2015-04-23

申请号：US14056144

申请日：2013-10-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Hoon Kim ,  Xunyuan Zhang

IPC: H01L21/28 ,  H01L29/49 ,  H01L27/092 ,  H01L29/51

CPC classification number: H01L27/0924 ,  H01L21/28008 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517

Abstract: Approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer and a barrier layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, wherein the high-k layer, barrier layer, and WFM are each recessed to a desired height within the recesses, and a metal material (e.g., Tungsten) formed within each recess. By providing a WFM chamfer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth improves fill-in of the metal material, which lowers gate resistance in the device.

Abstract translation: 公开了形成半导体器件的替代金属栅极（RMG）的方法。 具体地提供了在衬底上形成的p沟道场效应晶体管（p-FET）和n沟道场效应晶体管（n-FET），其中形成有凹部的p-FET和n-FET， 高k层和在每个凹槽内形成的阻挡层，选择性地生长在n-FET的凹槽内的功函数金属（WFM），其中高k层，势垒层和WFM各自凹入到期望的 在凹部内的高度，以及形成在每个凹部内的金属材料（例如，钨）。 通过在该方法中较早提供WFM倒角，减少了掩模材料填充到每个浇口凹槽中的风险。 此外，选择性WFM生长改善了金属材料的填充，这降低了器件中的栅极电阻。

公开(公告)号：US20150021704A1

公开(公告)日：2015-01-22

申请号：US13944403

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Hoon Kim

IPC: H01L21/28 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/28088 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795

Abstract: An improved method and structure for fabrication of replacement metal gate (RMG) field effect transistors is disclosed. P-type field effect transistor (PFET) gate cavities are protected while N work function metals are deposited in N-type field effect transistor (NFET) gate cavities.

Abstract translation: 公开了用于制造替代金属栅极（RMG）场效应晶体管的改进的方法和结构。 P型场效应晶体管（PFET）栅极腔被保护，而N型功能金属沉积在N型场效应晶体管（NFET）栅极腔中。

公开(公告)号：US20140167264A1

公开(公告)日：2014-06-19

申请号：US13714049

申请日：2012-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Paul R. Besser ,  Mark V. Raymond ,  Valli Arunachalam ,  Hoon Kim

IPC: H01L21/283 ,  H01L29/49

CPC classification number: H01L29/4916 ,  H01L21/28518 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the sidewalls of each fin. In the method, the metal film stack is annealed to form a metal silicide film over the sidewalls of each fin.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括提供半导体衬底并在半导体衬底上形成翅片。 每个翅片形成有侧壁。 该方法还包括在每个翅片的侧壁上共形沉积金属膜堆叠。 在该方法中，金属膜堆叠被退火以在每个翅片的侧壁上形成金属硅化物膜。

公开(公告)号：US20140124876A1

公开(公告)日：2014-05-08

申请号：US13670251

申请日：2012-11-06

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Hoon Kim ,  Kisik Choi

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L21/28088 ,  H01L29/4966

Abstract: A PFET-based semiconductor gate structure providing a midgap work function for threshold voltage control between that of a NFET and a PFET is created by including an annealed layer of relatively thick TiN to dominate and shift the overall work function down from that of PFET. The structure has a PFET base covered with a high-k dielectric, a layer of annealed TiN, a layer of unannealed TiN, a thin barrier over the unannealed TiN, and n-type metal over the thin barrier.

Abstract translation: 通过包括相对较厚的TiN的退火层来支配并将整个功函数从PFET的整个功能转移到底部，从而产生用于在NFET和PFET之间进行阈值电压控制的中隙工作功能的基于PFET的半导体栅极结构。 该结构具有覆盖有高k电介质层，退火TiN层，未退火TiN层，未退火TiN上的薄势垒和薄势垒上的n型金属的PFET基极。

公开(公告)号：US10410933B2

公开(公告)日：2019-09-10

申请号：US15602225

申请日：2017-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Hui Zang ,  Guowei Xu

IPC: H01L21/3213 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02

Abstract: This disclosure relates to a method of replacement metal gate patterning for nanosheet devices including: forming a first and a second nanosheet stack on a substrate, the first and the second nanosheet stacks being adjacent to each other and each including vertically adjacent nanosheets separated by a distance; depositing a first metal surrounding the first nanosheet stack and a second portion of the first metal surrounding the second nanosheet stack; forming an isolation region between the first nanosheet stack and the second nanosheet stack; removing the second portion of the first metal surrounding the second nanosheet stack with an etching process, the isolation region preventing the etching process from reaching the first portion of the first metal and thereby preventing removal of the first portion of the first metal; and depositing a second metal surrounding each of the nanosheets of the second nanosheet stack.