公开(公告)号：US07897513B2

公开(公告)日：2011-03-01

申请号：US11770593

申请日：2007-06-28

申请人： Haowen Bu ,  Shashank Ekbote ,  Juanita Deloach

发明人： Haowen Bu ,  Shashank Ekbote ,  Juanita Deloach

IPC分类号： H01L21/44

CPC分类号： H01L21/28518

摘要： The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing a metal layer on the substrate. The metal layer is annealed within a first temperature range and for a first dwell time of about 10 milliseconds or less to react at least a portion of the metal with the silicon to form a silicide. An unreacted portion of the metal is removed from the substrate. The silicide is annealed within a second temperature range for a second dwell time of about 10 milliseconds or less.

摘要翻译： 本申请涉及形成金属硅化物层的方法。 该方法包括提供包括硅的衬底并在衬底上沉积金属层。 金属层在第一温度范围内退火，并且在约10毫秒或更短的第一停留时间内使至少一部分金属与硅反应形成硅化物。 将金属的未反应部分从基材上除去。 硅化物在第二温度范围内退火约10毫秒或更短的第二停留时间。

公开(公告)号：US07855111B2

公开(公告)日：2010-12-21

申请号：US12538048

申请日：2009-08-07

申请人： Haowen Bu ,  Shaofeng Yu ,  Angelo Pinto ,  Ajith Varghese

发明人： Haowen Bu ,  Shaofeng Yu ,  Angelo Pinto ,  Ajith Varghese

IPC分类号： H01L21/8238 ,  H01L27/118

CPC分类号： H01L21/26506 ,  H01L21/187 ,  H01L21/324 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/045 ,  H01L29/665

摘要： Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.

摘要翻译： 用于CMOS IC的混合取向技术（HOT）衬底包括用于NMOS的（100）取向硅区域和用于优化各个MOS晶体管中的载流子迁移率的用于PMOS的（110）区域。 （100）和（110）区域之间的边界区域必须足够窄以支持高栅极密度和SRAM单元。 本发明提供一种形成含有两个不同硅晶格取向的区域的HOT衬底的方法，边界形貌小于40纳米宽。 从（100）衬底晶片和（110）DBS层的直接硅键合（DSB）晶片开始，DSB层中的NMOS区域被双注入物非晶化，并通过固相外延（100）取向（100）取向重结晶 SPE）。 退火期间的晶体缺陷通过晶片顶表面上的低温氧化物层来防止。 还公开了用本发明方法形成的集成电路。

公开(公告)号：US20100159665A1

公开(公告)日：2010-06-24

申请号：US12478512

申请日：2009-06-04

申请人： Jiong-Ping Lu ,  Haowen Bu ,  Clint Montgomery

发明人： Jiong-Ping Lu ,  Haowen Bu ,  Clint Montgomery

IPC分类号： H01L21/02

CPC分类号： H01L28/40 ,  H01L27/1085

摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layer 148 located over a gate electrode layer 143, a capacitor 170 located on the recrystallized polysilicon layer 148. The capacitor 170, in this embodiment, includes a first electrode 173, an insulator 175 located over the first electrode 173, and a second electrode 178 located over the insulator 175.

摘要翻译： 本发明提供一种半导体器件及其制造方法以及包括半导体器件的集成电路。 除了其他元件之外，半导体器件包括位于栅电极层143上的再结晶多晶硅层148，位于再结晶多晶硅层148上的电容器170.在该实施例中，电容器170包括第一电极173，绝缘体175 位于第一电极173上方，以及位于绝缘体175上方的第二电极178。

公开(公告)号：US07700467B2

公开(公告)日：2010-04-20

申请号：US11872333

申请日：2007-10-15

申请人： Haowen Bu ,  Scott Gregory Bushman ,  Periannan Chidambaram

发明人： Haowen Bu ,  Scott Gregory Bushman ,  Periannan Chidambaram

IPC分类号： H01L21/265

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L22/12 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636

摘要： Exemplary embodiments provide methods for implementing an ultra-high temperature (UHT) anneal on silicon germanium (SiGe) semiconductor materials by co-implanting carbon into the SiGe material prior to the UHT anneal. Specifically, the carbon implantation can be employed to increase the melting point of the SiGe material such that an ultra high temperature can be used for the subsequent anneal process. Wafer warpage can then be reduced during the UHT anneal process and potential lithographic mis-alignment for subsequent processes can be reduced. Exemplary embodiments further provide an inline control method, wherein the wafer warpage can be measured to determine the litho-mis-alignment and thus to control the fabrication process. In various embodiments, the disclosed methods can be employed for the fabrication of source/drain extension regions and/or source/drain regions of transistor devices, and/or for the fabrication of base regions of bipolar transistors.

摘要翻译： 示例性实施例提供了通过在UHT退火之前将碳并入到SiGe材料中来在硅锗（SiGe）半导体材料上实现超高温（UHT）退火的方法。 具体地，可以使用碳注入来增加SiGe材料的熔点，使得可以将超高温用于随后的退火工艺。 然后可以在UHT退火工艺期间降低晶片翘曲，并且可以减少后续工艺的潜在光刻误差。 示例性实施例还提供了一种在线控制方法，其中可以测量晶片翘曲以确定光学错误对准，从而控制制造工艺。 在各种实施例中，所公开的方法可用于制造晶体管器件的源极/漏极延伸区域和/或源极/漏极区域，和/或用于制造双极晶体管的基极区域。

公开(公告)号：US20100032813A1

公开(公告)日：2010-02-11

申请号：US12538280

申请日：2009-08-10

申请人： Deborah J. Riley ,  Haowen Bu ,  Brian Edward Hornung

发明人： Deborah J. Riley ,  Haowen Bu ,  Brian Edward Hornung

IPC分类号： H01L23/29 ,  H01L21/31

CPC分类号： H01L21/02238 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/31654 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/7833

摘要： A semiconductor device, such as an integrated circuit, has an oxide chemically grown on a silicon surface, and densified by annealing at, e.g., 950° C. for 4 to 5 seconds in an N2 ambient, or at an equivalent thermal profile in a similarly non-oxidizing ambient. The densified chemical oxide has an etch rate the same as that of thermally grown silicon dioxide in common etchants used in IC fabrication.

摘要翻译： 诸如集成电路的半导体器件具有在硅表面上化学生长的氧化物，并且通过在例如950℃下在N 2环境中退火4至5秒或在等温热分布中致密化 类似的非氧化环境。 致密化学氧化物的蚀刻速率与用于IC制造的常用蚀刻剂中的热生长二氧化硅的蚀刻速率相同。

公开(公告)号：US20090170256A1

公开(公告)日：2009-07-02

申请号：US12206456

申请日：2008-09-08

申请人： Srinivasan Chakravarthi ,  Haowen Bu ,  Periannan Chidambaram

发明人： Srinivasan Chakravarthi ,  Haowen Bu ,  Periannan Chidambaram

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of forming a transistor comprising forming a gate structure over an n-type semiconductor body and forming recesses substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown in the recesses and a silicon cap layer is formed over the silicon germanium. Further introduction of impurities into the silicon germanium to increase the melting point thereof and implanting p-type source/drain regions in the semiconductor body is included in the method. The method concludes with performing a high temperature thermal treatment.

摘要翻译： 一种形成晶体管的方法，包括在n型半导体本体上形成栅极结构，并形成与半导体本体中的栅极结构基本对准的凹槽。 然后在凹槽中外延生长硅锗，并在硅锗上形成硅帽层。 在该方法中包括将杂质进一步引入硅锗以增加其熔点并在半导体本体中注入p型源/漏区。 该方法的结论是进行高温热处理。

公开(公告)号：US07514331B2

公开(公告)日：2009-04-07

申请号：US11422952

申请日：2006-06-08

申请人： Jong Shik Yoon ,  Amitava Chatterjee ,  Haowen Bu

发明人： Jong Shik Yoon ,  Amitava Chatterjee ,  Haowen Bu

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/2652 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spacers of a gate structure located adjacent to the source and drain regions. The method further comprises depositing a second oxide layer selectively on the exposed source and drain regions and then removing lateral segments of the silicon nitride sidewall spacers.

摘要翻译： 一种制造半导体器件的方法，包括去除沉积在半导体衬底上的第一氧化物层，从而暴露衬底的源极和漏极区域。 第一氧化物层被配置为用于形成邻近源极和漏极区的栅极结构的氮化硅侧壁间隔物的蚀刻停止。 该方法还包括在暴露的源极和漏极区上选择性地沉积第二氧化物层，然后去除氮化硅侧壁间隔物的侧向部分。

公开(公告)号：US07402535B2

公开(公告)日：2008-07-22

申请号：US10902657

申请日：2004-07-28

申请人： Mahalingam Nandakumar ,  Haowen Bu

发明人： Mahalingam Nandakumar ,  Haowen Bu

IPC分类号： H01L21/469 ,  H01L21/31

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located between them. A first stress-inducing layer 190 is placed on a backside of the semiconductor wafer substrate 110 and is subjected to a thermal anneal to cause a stress to form in the channel region 175.

摘要翻译： 本发明提供的方法包括在位于半导体晶片衬底110的前侧的栅极结构130附近的半导体晶片衬底110中形成源/漏区170。 源极/漏极区170具有位于它们之间的沟道区175。 第一应力诱导层190放置在半导体晶片衬底110的背面，并进行热退火以在沟道区175中形成应力。

公开(公告)号：US07341933B2

公开(公告)日：2008-03-11

申请号：US11007569

申请日：2004-12-08

申请人： Shaofeng Yu ,  Haowen Bu ,  Jiong-Ping Lu ,  Lindsey Hall

发明人： Shaofeng Yu ,  Haowen Bu ,  Jiong-Ping Lu ,  Lindsey Hall

IPC分类号： H01L21/3205

CPC分类号： H01L29/66545 ,  H01L29/51 ,  H01L29/66507 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes providing a capped polysilicon gate electrode (290) over a substrate (210), the capped polysilicon gate electrode (290) including a buffer layer (260) located between a polysilicon gate electrode layer (250) and a protective layer (270). The method further includes forming source/drain regions (710) in the substrate (210) proximate the capped polysilicon gate electrode (290), removing the protective layer (270) and the buffer layer (260), and siliciding the polysilicon gate electrode layer (250) to form a silicided gate electrode (1110).

摘要翻译： 本发明提供一种制造半导体器件的方法和集成电路的制造方法。 制造半导体器件的方法以及其他步骤包括在衬底（210）上提供封盖的多晶硅栅电极（290），封装的多晶硅栅电极（290）包括位于多晶硅栅电极 层（250）和保护层（270）。 该方法还包括在靠近封盖的多晶硅栅极（290）的基板（210）中形成源/漏区（710），去除保护层（270）和缓冲层（260），并且将多晶硅栅电极层 （250），以形成硅化物栅电极（1110）。

公开(公告)号：US20070072364A1

公开(公告)日：2007-03-29

申请号：US11549375

申请日：2006-10-13

申请人： Mark Visokay ,  Luigi Colombo ,  James Chambers ,  Antonio Rotondaro ,  Haowen Bu

发明人： Mark Visokay ,  Luigi Colombo ,  James Chambers ,  Antonio Rotondaro ,  Haowen Bu

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L21/28185 ,  H01L21/02148 ,  H01L21/02271 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/3162 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L29/517 ,  H01L29/518

摘要： Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.

摘要翻译： 公开了用于处理沉积的栅极电介质材料的方法，其中沉积的电介质经受一个或多个非氧化退火以致密化材料，一个或多个氧化退火以减轻材料缺陷，以及氮化过程以将氮引入 栅电介质。 可以在氮化之前和/或之后进行退火以减轻沉积和/或氮化缺陷并致密材料，同时减轻在栅极电介质和半导体衬底之间的界面处形成不想要的低介电常数氧化物。