Process for creating piezo-electric mirrors in package

    公开(公告)号:US10969574B2

    公开(公告)日:2021-04-06

    申请号:US16072157

    申请日:2016-04-01

    Abstract: Embodiments of the invention include a piezo-electric mirror in an microelectronic package and methods of forming the package. According to an embodiment the microelectronic package may include an organic substrate with a cavity formed in the organic substrate. In some embodiments, an actuator is anchored to the organic substrate and extends over the cavity. For example, the actuator may include a first electrode and a piezo-electric layer formed on the first electrode. A second electrode may be formed on the piezo-electric layer. Additionally, a mirror may be formed on the actuator. Embodiments allow for the piezo-electric layer to be formed on an organic package substrate by using low temperature crystallization processes. For example, the piezo-electric layer may be deposited in an amorphous state. Thereafter, a laser annealing process that includes a pulsed laser may be used to crystallize the piezo-electric layer.

    THERMAL MANAGEMENT SOLUTIONS FOR EMBEDDED INTEGRATED CIRCUIT DEVICES

    公开(公告)号:US20200083135A1

    公开(公告)日:2020-03-12

    申请号:US16129243

    申请日:2018-09-12

    Abstract: An integrated circuit structure may be formed having a substrate, at least one integrated circuit device embedded in and electrically attached to the substrate, and a heat dissipation device in thermal contact with the integrated circuit device, wherein a first portion of the heat dissipation device extends into the substrate and wherein a second portion of the heat dissipation device extends over the substrate. In one embodiment, the heat dissipation device may comprise the first portion of the heat dissipation device formed from metallization within the substrate.

    Lithographacally defined vias for organic package substrate scaling

    公开(公告)号:US10381291B2

    公开(公告)日:2019-08-13

    申请号:US15745701

    申请日:2015-09-25

    Abstract: Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first dielectric layer and a photoresist layer is formed over the first dielectric layer and the via pad. Embodiments may then include patterning the photoresist layer to form a via opening over the via pad and depositing a conductive material into the via opening to form a via over the via pad. Embodiments may then includeremoving the photoresist layer and forming a second dielectric layer over the first dielectric layer, the via pad, and the via. For example a top surface of the second dielectric layer is formed above a top surface of the via in some embodiments. Embodiments may then include recessing the second dielectric layer to expose a top portion of the via.

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