公开(公告)号：US11430942B2

公开(公告)日：2022-08-30

申请号：US16021425

申请日：2018-06-28

Applicant: INTEL CORPORATION

Inventor： Kaan Oguz ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Chia-Ching Lin ,  Gary Allen

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01F41/30 ,  H01F10/32 ,  G11C11/16

Abstract: A multilayer free magnetic layer structure for spin-based magnetic memory is provided herein. The multilayer free magnetic structure is employed in a magnetic tunnel junction (MTJ) and includes antiferromagnetically coupled magnetic layers. In some cases, the antiferromagnetic coupling is mediated by RKKY interaction with a Ru, Ir, Mo, Cu, or Rh spacer layer. In some cases, low damping magnetic materials, such as CoFeB, FeB, or CoFeBMo are used for the antiferromagnetically coupled magnetic layers. By employing the multilayer free magnetic structure for the MTJ as variously described herein, the critical or switching current can be significantly reduced compared to, for example, an MTJ employing a single-layer free magnetic layer. Thus, higher device efficiencies can be achieved. In some cases, the magnetic layers of the multilayer free magnetic structure are perpendicular magnets, which can be employed, for example, in perpendicular spin-orbit torque (pSOT) memory devices.

公开(公告)号：US11410021B2

公开(公告)日：2022-08-09

申请号：US16175238

申请日：2018-10-30

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Dmitri Nikonov ,  Ian Young

IPC: G06N3/04 ,  H01L43/02 ,  H01L43/12 ,  H01F10/32 ,  H01F41/32 ,  H03K19/18 ,  H01L27/22 ,  H01L43/10

Abstract: Techniques are provided for implementing a recurrent neuron (RN) using magneto-electric spin orbit (MESO) logic. An RN implementing the techniques according to an embodiment includes a first MESO device to apply a threshold function to an input signal provided at a magnetization port of the MESO device, and scale the result by a first weighting factor supplied at an input port of the MESO device to generate an RN output signal. The RN further includes a second MESO device to receive the RN output signal at a magnetization port of the second MESO device and generate a scaled previous RN state value. The scaled previous state value is a scaled and time delayed version of the RN output signal based on a second weighting factor. The RN input signal is a summation of the scaled previous state value of the RN with weighted synaptic input signals provided to the RN.

公开(公告)号：US11374163B2

公开(公告)日：2022-06-28

申请号：US16012668

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-Ching Lin ,  Sasikanth Manipatruni ,  Dmitri Nikonov ,  Ian Young

IPC: H01L43/02 ,  G11C11/16 ,  H01L43/10

Abstract: A low power, energy efficient, nonvolatile, high-speed memory apparatus is provided that can function at extremely low temperatures (e.g., less than 30 degree Kelvin). The apparatus includes: a first structure comprising a magnet having free or unpinned magnetization; a second structure comprising Type-II multiferroic material, wherein the second structure is adjacent to the first structure; and an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the first structure.

公开(公告)号：US11362263B2

公开(公告)日：2022-06-14

申请号：US16024411

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Justin Brockman ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young

IPC: H01L43/02 ,  G11C11/16 ,  H01L43/12 ,  H01L43/10 ,  B82Y25/00

Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a magnetic tunnel junction (MTJ) device on a portion of the electrode. The electrode has a first SOC layer and a second SOC layer on a portion of the first SOC layer, where at least a portion of the first SOC layer at an interface with the second SOC layer includes oxygen.

公开(公告)号：US11281961B2

公开(公告)日：2022-03-22

申请号：US16121756

申请日：2018-09-05

Applicant: INTEL CORPORATION

Inventor： Dmitri Nikonov ,  Sasikanth Manipatruni ,  Ian Young

IPC: G06N3/04 ,  H03K3/03 ,  H03L7/099 ,  H01L23/66 ,  H05K1/02

Abstract: Techniques are provided for radio frequency interconnections between oscillators and transmission lines for oscillatory neural networks (ONNs). An ONN gate implementing the techniques according to an embodiment includes a transmission line, a first oscillator circuit tuned to a first frequency based on a first tuning voltage associated with a first synapse weight, and a first capacitive coupler to couple the first oscillator circuit to the transmission line to generate an oscillating signal in the transmission line. The ONN gate further includes a second oscillator circuit tuned to a second frequency based on a second tuning voltage associated with a second synapse weight, and a second capacitive coupler to couple the second oscillator circuit to the transmission line to adjust the oscillating signal in the transmission line such that the amplitude of the adjusted oscillating signal is associated with a degree of match between the first frequency and the second frequency.

公开(公告)号：US11048434B2

公开(公告)日：2021-06-29

申请号：US16147024

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Phil Knag ,  Gregory K. Chen ,  Huseyin Ekin Sumbul ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Abhishek Sharma ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G11C11/419 ,  G06F3/06 ,  G04F10/00 ,  G11C13/00 ,  G11C11/418 ,  G11C7/10 ,  G11C11/54

Abstract: A memory circuit has compute-in-memory (CIM) circuitry that performs computations based on time-to-digital conversion (TDC). The memory circuit includes an array of memory cells addressable with column address and row address. The memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value. A processing circuit determines a value of the multiple memory cells based on the digital value.

公开(公告)号：US20210143819A1

公开(公告)日：2021-05-13

申请号：US17152552

申请日：2021-01-19

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Patrick Morrow ,  Anurag Chaudhry

IPC: H03K19/00 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H03K19/18

Abstract: Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.

公开(公告)号：US10956813B2

公开(公告)日：2021-03-23

申请号：US16147109

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Ian A. Young ,  Ram Krishnamurthy ,  Sasikanth Manipatruni ,  Gregory K. Chen ,  Amrita Mathuriya ,  Abhishek Sharma ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul

IPC: G06N3/06 ,  G06N3/063 ,  G11C11/419 ,  G11C5/06 ,  H03M7/30 ,  G11C11/413 ,  G11C7/10 ,  G11C11/54 ,  G06N3/04

Abstract: An apparatus is described. The apparatus includes a compute in memory circuit. The compute in memory circuit includes a memory circuit and an encoder. The memory circuit is to provide 2m voltage levels on a read data line where m is greater than 1. The memory circuit includes storage cells sufficient to store a number of bits n where n is greater than m. The encoder is to receive an m bit input and convert the m bit input into an n bit word that is to be stored in the memory circuit, where, the m bit to n bit encoding performed by the encoder creates greater separation between those of the voltage levels that demonstrate wider voltage distributions on the read data line than others of the voltage levels.

公开(公告)号：US10944399B2

公开(公告)日：2021-03-09

申请号：US15779074

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Patrick Morrow ,  Anurag Chaudhry

IPC: H03K19/00 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H03K19/18

Abstract: Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.

公开(公告)号：US10910556B2

公开(公告)日：2021-02-02

申请号：US16081001

申请日：2016-03-29

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Ravi Pillarisetty ,  Uygar E. Avci

IPC: H01L43/10 ,  G11B5/73 ,  G11C11/16 ,  H01F10/32 ,  G11B5/72

Abstract: Described is an apparatus which comprises: a heat spreading layer; a first transition metal layer adjacent to the heat spreading layer; and a magnetic recording layer adjacent to the first transition metal layer. Described is an apparatus which comprises: a first electrode; a magnetic junction having a free magnet; and one or more layers of Jahn-Teller material adjacent to the first electrode and the free magnet of the magnetic junction.