公开(公告)号：US10204851B2

公开(公告)日：2019-02-12

申请号：US15900696

申请日：2018-02-20

Applicant: INTEL CORPORATION

Inventor： Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/50 ,  H01L21/768 ,  H01L23/538

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

公开(公告)号：US20170148714A1

公开(公告)日：2017-05-25

申请号：US15369659

申请日：2016-12-05

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US09542522B2

公开(公告)日：2017-01-10

申请号：US14491693

申请日：2014-09-19

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Dae-Woo Kim

IPC: H01L23/48 ,  H01L21/336 ,  G06F17/50 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/5381 ,  G06F17/5077 ,  H01L21/4857 ,  H01L21/76802 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及互连路由配置和相关技术。 在一个实施例中，一种装置包括基板，设置在基板上并具有第一多个迹线的第一布线层和与第一布线层直接相邻设置且具有第二多个迹线的第二布线层，其中第一布线层 第一多个迹线的迹线具有大于第二多个迹线的第二迹线的宽度的宽度。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09515017B2

公开(公告)日：2016-12-06

申请号：US14943880

申请日：2015-11-17

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

IPC: H01L23/52 ,  H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于集成电路（IC）组件中用于串扰缓解的地面通过群集的技术和配置。 在一些实施例中，IC封装组件可以包括被配置为在管芯和第二封装衬底之间路由输入/输出（I / O）信号和接地的第一封装衬底。 第一封装衬底可以包括设置在第一封装衬底的一侧上的多个触点和相同的通孔层的至少两个接地通孔，并且所述至少两个接地通孔可以形成一组接地通孔， 个人联系。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160204049A1

公开(公告)日：2016-07-14

申请号：US15046280

申请日：2016-02-17

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

IPC: H01L23/482 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L23/5385 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/4821 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

公开(公告)号：US20160104632A1

公开(公告)日：2016-04-14

申请号：US14974726

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tao Wu ,  Zhiguo Qian ,  Kemal Aygun

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1517 ,  H01L2924/15311

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described.

Abstract translation: 这里描述的一些实施例包括形成这种装置的装置和方法。 一个这样的实施例可以包括具有要耦合到半导体管芯的焊盘的布线布置，其中第一迹线耦合到焊盘之间的第一焊盘，以及耦合到焊盘之间的第二焊盘的第二迹线。 第一和第二迹线可以具有不同的厚度。 描述包括附加装置和方法的其他实施例。